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The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate

TL Wu, D Marcon, B De Jaeger, M Van Hove, B Bakeroot, DN Lin, S Stoffels, XW Kang, R Roelofs, G Groeseneken, et al.
(2015) Proceedings of the International Symposium on Power Semiconductor Devices & ICs. In Proceedings of the International Symposium on Power Semiconductor Devices & ICs p.225-228
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Abstract
The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (V-TH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150 degrees C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nmthick PE-ALD SiN gate dielectric.
Keywords
GAN MIS-HEMTS, AlGaN/GaN, SILICON, recessed gate, gate dielectric, PE-ALD SiN, interface states, border traps, depletion mode, enhacement mode, TRAPS, INTERFACE

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MLA
Wu, TL, et al. “The Impact of the Gate Dielectric Quality in Developing Au-Free D-Mode and E-Mode Recessed Gate AlGaN/GaN Transistors on a 200mm Si Substrate.” Proceedings of the International Symposium on Power Semiconductor Devices & ICs, IEEE, 2015, pp. 225–28.
APA
Wu, T., Marcon, D., De Jaeger, B., Van Hove, M., Bakeroot, B., Lin, D., … Decoutere, S. (2015). The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate. Proceedings of the International Symposium on Power Semiconductor Devices & ICs, 225–228. New York, NY, USA: IEEE.
Chicago author-date
Wu, TL, D Marcon, B De Jaeger, M Van Hove, B Bakeroot, DN Lin, S Stoffels, et al. 2015. “The Impact of the Gate Dielectric Quality in Developing Au-Free D-Mode and E-Mode Recessed Gate AlGaN/GaN Transistors on a 200mm Si Substrate.” In Proceedings of the International Symposium on Power Semiconductor Devices & ICs, 225–28. New York, NY, USA: IEEE.
Chicago author-date (all authors)
Wu, TL, D Marcon, B De Jaeger, M Van Hove, B Bakeroot, DN Lin, S Stoffels, XW Kang, R Roelofs, G Groeseneken, and S Decoutere. 2015. “The Impact of the Gate Dielectric Quality in Developing Au-Free D-Mode and E-Mode Recessed Gate AlGaN/GaN Transistors on a 200mm Si Substrate.” In Proceedings of the International Symposium on Power Semiconductor Devices & ICs, 225–228. New York, NY, USA: IEEE.
Vancouver
1.
Wu T, Marcon D, De Jaeger B, Van Hove M, Bakeroot B, Lin D, et al. The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate. In: Proceedings of the International Symposium on Power Semiconductor Devices & ICs. New York, NY, USA: IEEE; 2015. p. 225–8.
IEEE
[1]
T. Wu et al., “The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate,” in Proceedings of the International Symposium on Power Semiconductor Devices & ICs, Hong Kong, PEOPLES R CHINA, 2015, pp. 225–228.
@inproceedings{7153016,
  abstract     = {{The selection of the gate dielectric is one of the most critical stability issues in recessed gate AlGaN/GaN transistors. In this work, we show that the quality of the gate dielectric has a strong impact on: 1) the threshold voltage (V-TH) hysteresis, 2) the drain current reduction for enhancement mode devices, and 3) the forward gate bias TDDB (time dependent dielectric breakdown). It will be shown that the VTH hysteresis and the current reduction can be minimized by using a dielectric with lower interface state density (Dit) and less border traps, e.g., a PE-ALD SiN dielectric. Furthermore, the 0.01% failures at 20 years TDDB requirement at 150 degrees C for a large power device, e.g., gate width Wg=36mm, necessitates the use of at least a 25nmthick PE-ALD SiN gate dielectric.}},
  author       = {{Wu, TL and Marcon, D and De Jaeger, B and Van Hove, M and Bakeroot, B and Lin, DN and Stoffels, S and Kang, XW and Roelofs, R and Groeseneken, G and Decoutere, S}},
  booktitle    = {{Proceedings of the International Symposium on Power Semiconductor Devices & ICs}},
  isbn         = {{978-1-4799-6261-7}},
  issn         = {{1063-6854}},
  keywords     = {{GAN MIS-HEMTS,AlGaN/GaN,SILICON,recessed gate,gate dielectric,PE-ALD SiN,interface states,border traps,depletion mode,enhacement mode,TRAPS,INTERFACE}},
  language     = {{eng}},
  location     = {{Hong Kong, PEOPLES R CHINA}},
  pages        = {{225--228}},
  publisher    = {{IEEE}},
  title        = {{The impact of the gate dielectric quality in developing Au-free D-mode and E-mode recessed gate AlGaN/GaN transistors on a 200mm Si substrate}},
  year         = {{2015}},
}
Web of Science
Times cited: