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High-level synthesis for FPGAs, the Swiss army knife for high-performance computing

Erik D'Hollander UGent (2016) Seminaires de la Maison de la Simulation.
abstract
Field programmable gate arrays or FPGAs are the Swiss army knife of the compute accelerators. They are highly flexible, have many capabilities, operate at low power and yet have their limitations and are sometimes not easy to handle. In this talk we address the FPGA as an algorithm in hardware and discuss the techniques and tools for efficient hardware-software codesign. After more than two decades of research to raise the abstraction level, high-level synthesis tools now have reached the maturity to be used by the knowledgeable programmer. The architectural views include the OpenCL as well as the C-language with directives oriented paradigms. We will describe the characteristics, parameters and metrics of the logic fabric which are essential to obtain good performance. Next the multiple facets of the design exploration are illustrated with respect to balancing the resources, optimizing the interface and adapting the algorithm for execution on an FPGA. From this discussion we will be able to draw conclusions about the challenges and opportunities for this Swiss army knife accelerator in the arena of high-performance computing.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
field programmable gate arrays, high-level synthesis, FPGAs, HLS, design exploration, accelerator
in
Seminaires de la Maison de la Simulation
pages
62 pages
publisher
Maison de la Simulation, Paris, France
place of publication
Saclay, France
conference name
Programming models for FPGA
conference location
Paris, France
conference start
2016-01-19
conference end
2016-01-19
language
English
UGent publication?
yes
classification
C3
additional info
Invited talk
copyright statement
I have retained and own the full copyright for this publication
id
7047860
handle
http://hdl.handle.net/1854/LU-7047860
alternative location
http://www.maisondelasimulation.fr/Phocea/Vie_des_labos/Seminaires/index.php?id=110
date created
2016-01-22 13:22:29
date last changed
2017-01-02 09:53:29
@inproceedings{7047860,
  abstract     = {Field programmable gate arrays or FPGAs are the Swiss army knife of the compute accelerators. They are highly flexible, have many capabilities, operate at low power and yet have their limitations and are sometimes not easy to handle.
In this talk we address the FPGA as an algorithm in hardware and discuss the techniques and tools for efficient hardware-software codesign. After more than two decades of research to raise the abstraction level, high-level synthesis tools now have reached the maturity to be used by the knowledgeable programmer. The architectural views include the OpenCL as well as the C-language with directives oriented paradigms.
We will describe the characteristics, parameters and metrics of the logic fabric which are essential to obtain good performance. Next the multiple facets of the design exploration are illustrated with respect to balancing the resources, optimizing the interface and  adapting the algorithm for execution on an FPGA. From this discussion we will be able to draw conclusions about the challenges and opportunities for this Swiss army knife accelerator in the arena of high-performance computing.},
  author       = {D'Hollander, Erik},
  booktitle    = {Seminaires de la Maison de la Simulation},
  keyword      = {field programmable gate arrays,high-level synthesis,FPGAs,HLS,design exploration,accelerator},
  language     = {eng},
  location     = {Paris, France},
  pages        = {62},
  publisher    = {Maison de la Simulation, Paris, France},
  title        = {High-level synthesis for FPGAs, the Swiss army knife for high-performance computing},
  url          = {http://www.maisondelasimulation.fr/Phocea/Vie\_des\_labos/Seminaires/index.php?id=110},
  year         = {2016},
}

Chicago
D’Hollander, Erik. 2016. “High-level Synthesis for FPGAs, the Swiss Army Knife for High-performance Computing.” In Seminaires De La Maison De La Simulation. Saclay, France: Maison de la Simulation, Paris, France.
APA
D’Hollander, E. (2016). High-level synthesis for FPGAs, the Swiss army knife for high-performance computing. Seminaires de la Maison de la Simulation. Presented at the Programming models for FPGA, Saclay, France: Maison de la Simulation, Paris, France.
Vancouver
1.
D’Hollander E. High-level synthesis for FPGAs, the Swiss army knife for high-performance computing. Seminaires de la Maison de la Simulation. Saclay, France: Maison de la Simulation, Paris, France; 2016.
MLA
D’Hollander, Erik. “High-level Synthesis for FPGAs, the Swiss Army Knife for High-performance Computing.” Seminaires De La Maison De La Simulation. Saclay, France: Maison de la Simulation, Paris, France, 2016. Print.