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Abstract
Modern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore’s Law). Existing many-core power management techniques such as chip-wide/per-core DVFS, and core and cache adaptation are quite effective in isolation at moderate to high power budgets. However, for future many-core chip, the existing techniques do not scale well to large core counts, small time slices and stringent power budgets. We need a new solution that combines different adaptation and reconfiguration techniques. In this paper, we present Chrysso, an integrated, scalable and low-overhead power management framework. Chrysso consists of a three-step process: leveraging simple analytical performance and power models, pruning the search space early using local Pareto front generation, followed by global utility-based power allocation. This ensures scalable and effective dynamic adaptation of many-core processors at short time scales along multiple axes, including core, cache and per-core DVFS adaptations. By integrating multiple power management techniques into a common methodology, Chrysso provides significant performance improvements over isolated mechanisms within a given power budget without power-gating cores. On a 64-core system, Chrysso improves system throughput by 1.6x and 1.9x over core-gating at stringent power envelops for multi-program (SPEC) and multi-threaded (PARSEC) workloads, respectively.
Keywords
analytical modeling, Many-core processor, microarchitecture reconfiguration, power management

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MLA
Jha, Sudhanshu, et al. “Chrysso: An Integrated Power Manager for Constrained Many-Core Processors.” Proceedings of the 12th ACM International Conference on Computing Frontiers (CF), ACM, 2015.
APA
Jha, S., Heirman, W., Falcon, A., Carlson, T., Van Craeynest, K., Tubella, J., … Eeckhout, L. (2015). Chrysso: an integrated power manager for constrained many-core processors. Proceedings of the 12th ACM International Conference on Computing Frontiers (CF). Presented at the 12th ACM International Conference on Computing Frontiers (CF), Ischia, Italy.
Chicago author-date
Jha, Sudhanshu, Wim Heirman, Ayose Falcon, Trevor Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio Gonzalez, and Lieven Eeckhout. 2015. “Chrysso: An Integrated Power Manager for Constrained Many-Core Processors.” In Proceedings of the 12th ACM International Conference on Computing Frontiers (CF). ACM.
Chicago author-date (all authors)
Jha, Sudhanshu, Wim Heirman, Ayose Falcon, Trevor Carlson, Kenzo Van Craeynest, Jordi Tubella, Antonio Gonzalez, and Lieven Eeckhout. 2015. “Chrysso: An Integrated Power Manager for Constrained Many-Core Processors.” In Proceedings of the 12th ACM International Conference on Computing Frontiers (CF). ACM.
Vancouver
1.
Jha S, Heirman W, Falcon A, Carlson T, Van Craeynest K, Tubella J, et al. Chrysso: an integrated power manager for constrained many-core processors. In: Proceedings of the 12th ACM International Conference on Computing Frontiers (CF). ACM; 2015.
IEEE
[1]
S. Jha et al., “Chrysso: an integrated power manager for constrained many-core processors,” in Proceedings of the 12th ACM International Conference on Computing Frontiers (CF), Ischia, Italy, 2015.
@inproceedings{6954058,
  abstract     = {{Modern microprocessors are increasingly power-constrained as a result of slowed supply voltage scaling (end of Dennard scaling) in conjunction with the transistor density scaling (Moore’s Law). Existing many-core power management techniques such as chip-wide/per-core DVFS, and core and cache adaptation are quite effective in isolation at moderate to high power budgets. However, for future many-core chip, the existing techniques do not scale well to large core counts, small time slices and stringent power budgets. We need a new solution that combines different adaptation and reconfiguration techniques.

In this paper, we present Chrysso, an integrated, scalable and low-overhead power management framework. Chrysso consists of a three-step process: leveraging simple analytical performance and power models, pruning the search space early using local Pareto front generation, followed by global utility-based power allocation. This ensures scalable and effective dynamic adaptation of many-core processors at short time scales along multiple axes, including core, cache and per-core DVFS adaptations. By integrating multiple power management techniques into a common methodology, Chrysso provides significant performance improvements over isolated mechanisms within a given power budget without power-gating cores. On a 64-core system, Chrysso improves system throughput by 1.6x and 1.9x over core-gating at stringent power envelops for multi-program (SPEC) and multi-threaded (PARSEC) workloads, respectively.}},
  author       = {{Jha, Sudhanshu and Heirman, Wim and Falcon, Ayose and Carlson, Trevor and Van Craeynest, Kenzo and Tubella, Jordi and Gonzalez, Antonio and Eeckhout, Lieven}},
  booktitle    = {{Proceedings of the 12th ACM International Conference on Computing Frontiers (CF)}},
  isbn         = {{978-1-4503-3358-0}},
  keywords     = {{analytical modeling,Many-core processor,microarchitecture reconfiguration,power management}},
  language     = {{eng}},
  location     = {{Ischia, Italy}},
  pages        = {{8}},
  publisher    = {{ACM}},
  title        = {{Chrysso: an integrated power manager for constrained many-core processors}},
  year         = {{2015}},
}