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Performance and resource modeling for FPGAs using high-level synthesis tools

Bruno da Silva UGent, An Braeken, Erik D'Hollander UGent and Abdellah Touhafi (2014) Advances in Parallel Computing. 25. p.523-531
abstract
High-performance computing with FPGAs is gaining momentum with the advent of sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by the input-output bandwidth, the code optimizations and the resource consumption, making the performance estimation a challenge. This paper proposes a performance model which extends the roofline model to take into account the resource consumption and the parameters used in the HLS tools. A strategy is developed which maximizes the performance and the resource utilization within the area of the FPGA. The model is used to optimize the design exploration of a class of window-based image processing application.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
High-Level Synthesis, FPGA, Roofline Model
in
Advances in Parallel Computing
editor
Michael Bader, Arndt Bode, Hans-Joachim Bungartz, Michael Gerndt, Gerhard Joubert and Frans Peters
volume
25
pages
523 - 531
publisher
IOS Press
place of publication
Amsterdam
conference name
Symposium ParaFPGA 2013, Parallel Computing with FPGAs
conference location
Munich, Germany
conference start
2013-09-10
conference end
2013-09-13
ISBN
978-1-61499-381-0
DOI
10.3233/978-1-61499-381-0-523
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
6926752
handle
http://hdl.handle.net/1854/LU-6926752
alternative location
http://ebooks.iospress.nl/publication/35920
date created
2015-09-10 17:28:01
date last changed
2017-01-02 09:52:26
@inproceedings{6926752,
  abstract     = {High-performance computing with FPGAs is gaining momentum with the advent of sophisticated High-Level Synthesis (HLS) tools. The performance of a design is impacted by the input-output bandwidth, the code optimizations and the resource consumption, making the performance estimation a challenge. This paper proposes a performance model which extends the roofline model to take into account the resource consumption and the parameters used in the HLS tools. A strategy is developed which maximizes the performance and the resource utilization within the area of the FPGA. The model is used to optimize the design exploration of a class of window-based image processing application.},
  author       = {da Silva, Bruno and Braeken, An and D'Hollander, Erik and Touhafi, Abdellah},
  booktitle    = {Advances in Parallel Computing},
  editor       = {Bader, Michael and Bode, Arndt and Bungartz, Hans-Joachim and Gerndt, Michael and Joubert, Gerhard and Peters, Frans},
  isbn         = {978-1-61499-381-0},
  keyword      = {High-Level Synthesis,FPGA,Roofline Model},
  language     = {eng},
  location     = {Munich, Germany},
  pages        = {523--531},
  publisher    = {IOS Press},
  title        = {Performance and resource modeling for FPGAs using high-level synthesis tools},
  url          = {http://dx.doi.org/10.3233/978-1-61499-381-0-523},
  volume       = {25},
  year         = {2014},
}

Chicago
da Silva, Bruno, An Braeken, Erik D’Hollander, and Abdellah Touhafi. 2014. “Performance and Resource Modeling for FPGAs Using High-level Synthesis Tools.” In Advances in Parallel Computing, ed. Michael Bader, Arndt Bode, Hans-Joachim Bungartz, Michael Gerndt, Gerhard Joubert, and Frans Peters, 25:523–531. Amsterdam: IOS Press.
APA
da Silva, B., Braeken, A., D’Hollander, E., & Touhafi, A. (2014). Performance and resource modeling for FPGAs using high-level synthesis tools. In M. Bader, A. Bode, H.-J. Bungartz, M. Gerndt, G. Joubert, & F. Peters (Eds.), Advances in Parallel Computing (Vol. 25, pp. 523–531). Presented at the Symposium ParaFPGA 2013, Parallel Computing with FPGAs, Amsterdam: IOS Press.
Vancouver
1.
da Silva B, Braeken A, D’Hollander E, Touhafi A. Performance and resource modeling for FPGAs using high-level synthesis tools. In: Bader M, Bode A, Bungartz H-J, Gerndt M, Joubert G, Peters F, editors. Advances in Parallel Computing. Amsterdam: IOS Press; 2014. p. 523–31.
MLA
da Silva, Bruno, An Braeken, Erik D’Hollander, et al. “Performance and Resource Modeling for FPGAs Using High-level Synthesis Tools.” Advances in Parallel Computing. Ed. Michael Bader et al. Vol. 25. Amsterdam: IOS Press, 2014. 523–531. Print.