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Coarse-grained reconfigurable array architectures

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Abstract
Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. Unlike VLIWs, CGRAs are designed to execute only the loops, which they can hence do more efficiently. This chapter discusses the basic principles of CGRAs and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.

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MLA
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. “Coarse-grained Reconfigurable Array Architectures.” Handbook of Signal Processing Systems. 2nd ed. Ed. Shuvra Bhattacharyya, Ed Deprettere, & Rainer Leupers. Springer, 2013. 553–592. Print.
APA
De Sutter, B., Raghavan, P., & Lambrechts, A. (2013). Coarse-grained reconfigurable array architectures. In S. Bhattacharyya, E. Deprettere, & R. Leupers (Eds.), Handbook of signal processing systems (2nd ed., pp. 553–592). Springer.
Chicago author-date
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. 2013. “Coarse-grained Reconfigurable Array Architectures.” In Handbook of Signal Processing Systems, ed. Shuvra Bhattacharyya, Ed Deprettere, and Rainer Leupers, 553–592. 2nd ed. Springer.
Chicago author-date (all authors)
De Sutter, Bjorn, Praveen Raghavan, and Andy Lambrechts. 2013. “Coarse-grained Reconfigurable Array Architectures.” In Handbook of Signal Processing Systems, ed. Shuvra Bhattacharyya, Ed Deprettere, and Rainer Leupers, 553–592. 2nd ed. Springer.
Vancouver
1.
De Sutter B, Raghavan P, Lambrechts A. Coarse-grained reconfigurable array architectures. In: Bhattacharyya S, Deprettere E, Leupers R, editors. Handbook of signal processing systems. 2nd ed. Springer; 2013. p. 553–92.
IEEE
[1]
B. De Sutter, P. Raghavan, and A. Lambrechts, “Coarse-grained reconfigurable array architectures,” in Handbook of signal processing systems, 2nd ed., S. Bhattacharyya, E. Deprettere, and R. Leupers, Eds. Springer, 2013, pp. 553–592.
@incollection{6847779,
  abstract     = {Coarse-Grained Reconfigurable Array (CGRA) architectures accelerate the same inner loops that benefit from the high ILP support in VLIW architectures. Unlike  VLIWs,  CGRAs  are  designed  to  execute  only  the  loops,  which  they  can hence do more efficiently. This chapter discusses the basic principles of CGRAs and the wide range of design options available to a CGRA designer, covering a large number of existing CGRA designs. The impact of different options on flexibility, performance, and power-efficiency is discussed, as well as the need for compiler support. The ADRES CGRA design template is studied in more detail as a use case to illustrate the need for design space exploration, for compiler support and for the manual fine-tuning of source code.},
  author       = {De Sutter, Bjorn and Raghavan, Praveen and Lambrechts, Andy},
  booktitle    = {Handbook of signal processing systems},
  editor       = {Bhattacharyya, Shuvra and Deprettere, Ed and Leupers, Rainer},
  isbn         = {9781461468585},
  language     = {eng},
  pages        = {553--592},
  publisher    = {Springer},
  title        = {Coarse-grained reconfigurable array architectures},
  url          = {http://www.springer.com/us/book/9781461468585},
  year         = {2013},
}