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FPGA Resource Estimation for Loop Controllers

Tom Degryse UGent, Harald Devos UGent and Dirk Stroobandt UGent (2008) p.9-15
abstract
High-level synthesis overcomes the high design effort required by using an FPGA by moving the hardware design to a higher abstraction level. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a large impact on the resulting hardware, but their impact is only known after the time-consuming synthesis steps. This hinders a fast designspace exploration.In this paper, we tackle this issue by estimating the performance of the hardware loop controller, an often overlooked component in other approaches. We present an equation based model to estimate the area and clock frequency of the loop controller during high-level synthesis. In our approach, we manage to keep estimation errors reasonably low, so our estimation model can be used during design space exploration. Due to its simplicity, the overhead is minimal, which is critical when lots of design variants need to be estimated.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
FPGA, high-level synthesis, estimation, loop controller
pages
7 pages
conference name
6th Workshop on Optimizations for DSP and Embedded Systems (ODES-6)
conference location
Boston
conference start
2008-04-06
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
681003
handle
http://hdl.handle.net/1854/LU-681003
date created
2009-06-05 16:19:11
date last changed
2016-12-19 15:36:22
@inproceedings{681003,
  abstract     = {High-level synthesis overcomes the high design effort required by using an FPGA by moving the hardware design to a higher abstraction level. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a large impact on the resulting hardware, but their impact is only known after the time-consuming synthesis steps. This hinders a fast designspace exploration.In this paper, we tackle this issue by estimating the performance of the hardware loop controller, an often overlooked component in other approaches. We present an equation based model to estimate the area and clock frequency of the loop controller during high-level synthesis. In our approach, we manage to keep estimation errors reasonably low, so our estimation model can be used during design space exploration. Due to its simplicity, the overhead is minimal, which is critical when lots of design variants need to be estimated.},
  author       = {Degryse, Tom and Devos, Harald and Stroobandt, Dirk},
  keyword      = {FPGA,high-level synthesis,estimation,loop controller},
  language     = {eng},
  location     = {Boston},
  pages        = {9--15},
  title        = {FPGA Resource Estimation for Loop Controllers},
  year         = {2008},
}

Chicago
Degryse, Tom, Harald Devos, and Dirk Stroobandt. 2008. “FPGA Resource Estimation for Loop Controllers.” In , 9–15.
APA
Degryse, T., Devos, H., & Stroobandt, D. (2008). FPGA Resource Estimation for Loop Controllers (pp. 9–15). Presented at the 6th Workshop on Optimizations for DSP and Embedded Systems (ODES-6).
Vancouver
1.
Degryse T, Devos H, Stroobandt D. FPGA Resource Estimation for Loop Controllers. 2008. p. 9–15.
MLA
Degryse, Tom, Harald Devos, and Dirk Stroobandt. “FPGA Resource Estimation for Loop Controllers.” 2008. 9–15. Print.