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Reducing the dynamic FPGA reconfiguration overhead with loop transformations

Tom Degryse UGent, Karel Bruneel UGent, Harald Devos UGent and Dirk Stroobandt UGent (2008) p.219-222
abstract
Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
pages
3 pages
conference name
Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems
conference location
L'Aquila, Italy
conference start
2008-07-13
conference end
2008-07-19
language
English
UGent publication?
yes
classification
C3
copyright statement
I have transferred the copyright for this publication to the publisher
id
680604
handle
http://hdl.handle.net/1854/LU-680604
date created
2009-06-05 15:05:10
date last changed
2016-12-19 15:35:09
@inproceedings{680604,
  abstract     = {Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.},
  author       = {Degryse, Tom and Bruneel, Karel and Devos, Harald and Stroobandt, Dirk},
  language     = {eng},
  location     = {L'Aquila, Italy},
  pages        = {219--222},
  title        = {Reducing the dynamic FPGA reconfiguration overhead with loop transformations},
  year         = {2008},
}

Chicago
Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Reducing the Dynamic FPGA Reconfiguration Overhead with Loop Transformations.” In , 219–222.
APA
Degryse, T., Bruneel, K., Devos, H., & Stroobandt, D. (2008). Reducing the dynamic FPGA reconfiguration overhead with loop transformations (pp. 219–222). Presented at the Fourth International Summer School on Advanced Computer Architecture and Compilation for Embedded Systems.
Vancouver
1.
Degryse T, Bruneel K, Devos H, Stroobandt D. Reducing the dynamic FPGA reconfiguration overhead with loop transformations. 2008. p. 219–22.
MLA
Degryse, Tom, Karel Bruneel, Harald Devos, et al. “Reducing the Dynamic FPGA Reconfiguration Overhead with Loop Transformations.” 2008. 219–222. Print.