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Reducing the dynamic FPGA reconfiguration overhead

Tom Degryse UGent, Karel Bruneel UGent, Harald Devos UGent and Dirk Stroobandt UGent (2008) p.53-56
abstract
Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
FPGAs, dynamic hardware generation, loop transformations
pages
4 pages
conference name
Architecture and Compilers for Embedded Systems
conference location
Edegem
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
679177
handle
http://hdl.handle.net/1854/LU-679177
date created
2009-06-05 10:56:46
date last changed
2016-12-19 15:35:17
@inproceedings{679177,
  abstract     = {Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.},
  author       = {Degryse, Tom and Bruneel, Karel and Devos, Harald and Stroobandt, Dirk},
  keyword      = {FPGAs,dynamic hardware generation,loop transformations},
  language     = {eng},
  location     = {Edegem},
  pages        = {53--56},
  title        = {Reducing the dynamic FPGA reconfiguration overhead},
  year         = {2008},
}

Chicago
Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Reducing the Dynamic FPGA Reconfiguration Overhead.” In , 53–56.
APA
Degryse, T., Bruneel, K., Devos, H., & Stroobandt, D. (2008). Reducing the dynamic FPGA reconfiguration overhead (pp. 53–56). Presented at the Architecture and Compilers for Embedded Systems.
Vancouver
1.
Degryse T, Bruneel K, Devos H, Stroobandt D. Reducing the dynamic FPGA reconfiguration overhead. 2008. p. 53–6.
MLA
Degryse, Tom, Karel Bruneel, Harald Devos, et al. “Reducing the Dynamic FPGA Reconfiguration Overhead.” 2008. 53–56. Print.