- Author
- Tom Degryse (UGent) , Karel Bruneel (UGent) , Harald Devos and Dirk Stroobandt (UGent)
- Organization
- Abstract
- Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.
- Keywords
- FPGAs, dynamic hardware generation, loop transformations
Downloads
-
P108 207.pdf
- full text
- |
- open access
- |
- |
- 116.48 KB
Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-679177
- MLA
- Degryse, Tom, et al. Reducing the Dynamic FPGA Reconfiguration Overhead. 2008, pp. 53–56.
- APA
- Degryse, T., Bruneel, K., Devos, H., & Stroobandt, D. (2008). Reducing the dynamic FPGA reconfiguration overhead. 53–56.
- Chicago author-date
- Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Reducing the Dynamic FPGA Reconfiguration Overhead.” In , 53–56.
- Chicago author-date (all authors)
- Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Reducing the Dynamic FPGA Reconfiguration Overhead.” In , 53–56.
- Vancouver
- 1.Degryse T, Bruneel K, Devos H, Stroobandt D. Reducing the dynamic FPGA reconfiguration overhead. In 2008. p. 53–6.
- IEEE
- [1]T. Degryse, K. Bruneel, H. Devos, and D. Stroobandt, “Reducing the dynamic FPGA reconfiguration overhead,” presented at the Architecture and Compilers for Embedded Systems, Edegem, 2008, pp. 53–56.
@inproceedings{679177,
abstract = {{Dynamic hardware generation reduces the number of FPGA resources needed and speeds up the application by optimizing the configuration for the exact problem at hand at run-time. If the problem changes, the system needs to be reconfigured. When this occurs too often, the total reconfiguration overhead is too high and the benefit of using dynamic hardware generation vanishes. Hence, it is important to minimize the number of reconfigurations.}},
author = {{Degryse, Tom and Bruneel, Karel and Devos, Harald and Stroobandt, Dirk}},
keywords = {{FPGAs,dynamic hardware generation,loop transformations}},
language = {{eng}},
location = {{Edegem}},
pages = {{53--56}},
title = {{Reducing the dynamic FPGA reconfiguration overhead}},
year = {{2008}},
}