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Reconfigurability-Aware Structural Mapping for LUT-based FPGAs

Karel Bruneel (UGent) and Dirk Stroobandt (UGent)
Author
Organization
Abstract
In many applications, subsequent tasks differ only in a specific set of parameters. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can be configured with an optimized configuration every time these parameter values change. This results in configurations that are smaller and faster than their generic counterparts. Unfortunately, the overhead involved in generating these configurations at run-time with conventional tools is very large. However, if the incoming tasks only differ in a set of parameter values, the use of Tunable LUT (TLUT) circuits can drastically reduce this overhead. A TLUT circuit is a LUT circuit in which the truth tables of the LUTs are expressed as a function of a set of parameters. At run-time the truth tables for a specific set of parameter values can rapidly be calculated by evaluating these functions. Up to now TLUT circuits had to be designed manually resulting in a huge design cost. This paper introduces TMAP2, a software tool based on conventional structural mapping that automatically generates a TLUT circuit starting from an arbitrary Boolean circuit. We have tested TMAP2 on a set of
Keywords
FPGA, reconfiguration, CAD

Citation

Please use this url to cite or link to this publication:

MLA
Bruneel, Karel, and Dirk Stroobandt. “Reconfigurability-Aware Structural Mapping for LUT-based FPGAs.” ReConFig’08 Proceedings. Ed. S. Ceballos. IEEE Computer Society, 2008. 223–228. Print.
APA
Bruneel, K., & Stroobandt, D. (2008). Reconfigurability-Aware Structural Mapping for LUT-based FPGAs. In S. Ceballos (Ed.), ReConFig’08 Proceedings (pp. 223–228). Presented at the 2008 International Conference on Reconfigurable Computing and FPGAs, IEEE Computer Society.
Chicago author-date
Bruneel, Karel, and Dirk Stroobandt. 2008. “Reconfigurability-Aware Structural Mapping for LUT-based FPGAs.” In ReConFig’08 Proceedings, ed. S. Ceballos, 223–228. IEEE Computer Society.
Chicago author-date (all authors)
Bruneel, Karel, and Dirk Stroobandt. 2008. “Reconfigurability-Aware Structural Mapping for LUT-based FPGAs.” In ReConFig’08 Proceedings, ed. S. Ceballos, 223–228. IEEE Computer Society.
Vancouver
1.
Bruneel K, Stroobandt D. Reconfigurability-Aware Structural Mapping for LUT-based FPGAs. In: Ceballos S, editor. ReConFig’08 Proceedings. IEEE Computer Society; 2008. p. 223–8.
IEEE
[1]
K. Bruneel and D. Stroobandt, “Reconfigurability-Aware Structural Mapping for LUT-based FPGAs,” in ReConFig’08 Proceedings, Cancun, 2008, pp. 223–228.
@inproceedings{677964,
  abstract     = {In many applications, subsequent tasks differ only in a specific set of parameters. Because of their reconfigurability, FPGAs (Field Programmable Gate Arrays) can be configured with an optimized configuration every time these parameter values change. This results in configurations that are smaller and faster than their generic counterparts. Unfortunately, the overhead involved in generating these configurations at run-time with conventional tools is very large. However, if the incoming tasks only differ in a set of parameter values, the use of Tunable LUT (TLUT) circuits can drastically reduce this overhead. A TLUT circuit is a LUT circuit in which the truth tables of the LUTs are expressed as a function of a set of parameters. At run-time the truth tables for a specific set of parameter values can rapidly be calculated by evaluating these functions. Up to now TLUT circuits had to be designed manually resulting in a huge design cost. This paper introduces TMAP2, a software tool based on conventional structural mapping that automatically generates a TLUT circuit starting from an arbitrary Boolean circuit. We have tested TMAP2 on a set of},
  author       = {Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {ReConFig'08 Proceedings},
  editor       = {Ceballos, S.},
  keywords     = {FPGA,reconfiguration,CAD},
  language     = {eng},
  location     = {Cancun},
  pages        = {223--228},
  publisher    = {IEEE Computer Society},
  title        = {Reconfigurability-Aware Structural Mapping for LUT-based FPGAs},
  year         = {2008},
}