Advanced search

Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead

Tom Degryse (UGent), Karel Bruneel (UGent), Harald Devos (UGent) and Dirk Stroobandt (UGent)
Author
Organization
Abstract
Dynamic hardware generation reduces the number of FPGA resources needed and speeds up an application by optimizing the FPGA configuration at run-time for the exact problem at hand. Because of the large overhead associated with dynamic hardware generation, it is important to minimize the number of reconfigurations. In this work, we present a technique to maximize the reuse of a configuration by means of loop transformations. Our approach builds on similar work on temporal data locality optimization. Our experiments on a matrix multiplication benchmark show that we can reduce the number of reconfigurations by an order of magnitude, making dynamic hardware
Keywords
FPGAs, dynamic hardware generation, loop transformations

Citation

Please use this url to cite or link to this publication:

Chicago
Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead.” In ReConFig’08 Proceedings, 133–138. IEEE.
APA
Degryse, T., Bruneel, K., Devos, H., & Stroobandt, D. (2008). Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead. ReConFig’08 Proceedings (pp. 133–138). Presented at the 2008 International Conference on Reconfigurable Computing and FPGAs, IEEE.
Vancouver
1.
Degryse T, Bruneel K, Devos H, Stroobandt D. Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead. ReConFig’08 Proceedings. IEEE; 2008. p. 133–8.
MLA
Degryse, Tom, Karel Bruneel, Harald Devos, et al. “Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead.” ReConFig’08 Proceedings. IEEE, 2008. 133–138. Print.
@inproceedings{677843,
  abstract     = {Dynamic hardware generation reduces the number of FPGA resources needed and speeds up an application by optimizing the FPGA configuration at run-time for the exact problem at hand. Because of the large overhead associated with dynamic hardware generation, it is important to minimize the number of reconfigurations. In this work, we present a technique to maximize the reuse of a configuration by means of loop transformations. Our approach builds on similar work on temporal data locality optimization. Our experiments on a matrix multiplication benchmark show that we can reduce the number of reconfigurations by an order of magnitude, making dynamic hardware},
  author       = {Degryse, Tom and Bruneel, Karel and Devos, Harald and Stroobandt, Dirk},
  booktitle    = {ReConFig'08 Proceedings},
  keyword      = {FPGAs,dynamic hardware generation,loop transformations},
  language     = {eng},
  location     = {Cancun, Mexico},
  pages        = {133--138},
  publisher    = {IEEE},
  title        = {Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead},
  year         = {2008},
}