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Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead

Tom Degryse UGent, Karel Bruneel UGent, Harald Devos UGent and Dirk Stroobandt UGent (2008) ReConFig'08 Proceedings. p.133-138
abstract
Dynamic hardware generation reduces the number of FPGA resources needed and speeds up an application by optimizing the FPGA configuration at run-time for the exact problem at hand. Because of the large overhead associated with dynamic hardware generation, it is important to minimize the number of reconfigurations. In this work, we present a technique to maximize the reuse of a configuration by means of loop transformations. Our approach builds on similar work on temporal data locality optimization. Our experiments on a matrix multiplication benchmark show that we can reduce the number of reconfigurations by an order of magnitude, making dynamic hardware
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
FPGAs, dynamic hardware generation, loop transformations
in
ReConFig'08 Proceedings
pages
6 pages
publisher
IEEE
conference name
2008 International Conference on Reconfigurable Computing and FPGAs
conference location
Cancun, Mexico
conference start
2008-12-03
conference end
2008-12-05
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
677843
handle
http://hdl.handle.net/1854/LU-677843
date created
2009-06-04 13:17:52
date last changed
2016-12-19 15:36:22
@inproceedings{677843,
  abstract     = {Dynamic hardware generation reduces the number of FPGA resources needed and speeds up an application by optimizing the FPGA configuration at run-time for the exact problem at hand. Because of the large overhead associated with dynamic hardware generation, it is important to minimize the number of reconfigurations. In this work, we present a technique to maximize the reuse of a configuration by means of loop transformations. Our approach builds on similar work on temporal data locality optimization. Our experiments on a matrix multiplication benchmark show that we can reduce the number of reconfigurations by an order of magnitude, making dynamic hardware},
  author       = {Degryse, Tom and Bruneel, Karel and Devos, Harald and Stroobandt, Dirk},
  booktitle    = {ReConFig'08 Proceedings},
  keyword      = {FPGAs,dynamic hardware generation,loop transformations},
  language     = {eng},
  location     = {Cancun, Mexico},
  pages        = {133--138},
  publisher    = {IEEE},
  title        = {Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead},
  year         = {2008},
}

Chicago
Degryse, Tom, Karel Bruneel, Harald Devos, and Dirk Stroobandt. 2008. “Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead.” In ReConFig’08 Proceedings, 133–138. IEEE.
APA
Degryse, T., Bruneel, K., Devos, H., & Stroobandt, D. (2008). Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead. ReConFig’08 Proceedings (pp. 133–138). Presented at the 2008 International Conference on Reconfigurable Computing and FPGAs, IEEE.
Vancouver
1.
Degryse T, Bruneel K, Devos H, Stroobandt D. Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead. ReConFig’08 Proceedings. IEEE; 2008. p. 133–8.
MLA
Degryse, Tom, Karel Bruneel, Harald Devos, et al. “Loop Transformations to Reduce the Dynamic FPGA Reconfiguration Overhead.” ReConFig’08 Proceedings. IEEE, 2008. 133–138. Print.