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Identification of dynamic circuit specialization opportunities in RTL code

Tom Davidson (UGent) , Elias Vansteenkiste (UGent) , Karel Heyse (UGent) , Karel Bruneel (UGent) and Dirk Stroobandt (UGent)
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Organization
Abstract
Dynamic Circuit Specialization (DCS) optimizes a Field-Programmable Gate Array (FPGA) design by assuming a set of its input signals are constant for a reasonable amount of time, leading to a smaller and faster FPGA circuit. When the signals actually change, a new circuit is loaded into the FPGA through runtime reconfiguration. The signals the design is specialized for are called parameters. For certain designs, parameters can be selected so the DCS implementation is both smaller and faster than the original implementation. However, DCS also introduces an overhead that is difficult for the designer to take into account, making it hard to determine whether a design is improved by DCS or not. This article presents extensive results on a profiling methodology that analyses Register-Transfer Level (RTL) implementations of applications to check if DCS would be beneficial. It proposes to use the functional density as a measure for the area efficiency of an implementation, as this measure contains both the overhead and the gains of a DCS implementation. The first step of the methodology is to analyse the dynamic behaviour of signals in the design, to find good parameter candidates. The overhead of DCS is highly dependent on this dynamic behaviour. A second stage calculates the functional density for each candidate and compares it to the functional density of the original design. The profiling methodology resulted in three implementations of a profiling tool, the DCS-RTL profiler. The execution time, accuracy, and the quality of each implementation is assessed based on data from 10 RTL designs. All designs, except for the two 16-bit adaptable Finite Impulse Response (FIR) filters, are analysed in 1 hour or less.
Keywords
Runtime Reconfiguration, Computer-Aided Design, RTL profiling, Dynamic circuit specialization, Field-Programmable Gate Array, SYSTEMS, PARTIAL RECONFIGURATION

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Please use this url to cite or link to this publication:

Chicago
Davidson, Tom, Elias Vansteenkiste, Karel Heyse, Karel Bruneel, and Dirk Stroobandt. 2015. “Identification of Dynamic Circuit Specialization Opportunities in RTL Code.” Acm Transactions on Reconfigurable Technology and Systems 8 (1).
APA
Davidson, Tom, Vansteenkiste, E., Heyse, K., Bruneel, K., & Stroobandt, D. (2015). Identification of dynamic circuit specialization opportunities in RTL code. ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 8(1).
Vancouver
1.
Davidson T, Vansteenkiste E, Heyse K, Bruneel K, Stroobandt D. Identification of dynamic circuit specialization opportunities in RTL code. ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS. 2015;8(1).
MLA
Davidson, Tom, Elias Vansteenkiste, Karel Heyse, et al. “Identification of Dynamic Circuit Specialization Opportunities in RTL Code.” ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 8.1 (2015): n. pag. Print.
@article{5939326,
  abstract     = {Dynamic Circuit Specialization (DCS) optimizes a Field-Programmable Gate Array (FPGA) design by assuming a set of its input signals are constant for a reasonable amount of time, leading to a smaller and faster FPGA circuit. When the signals actually change, a new circuit is loaded into the FPGA through runtime reconfiguration. The signals the design is specialized for are called parameters. For certain designs, parameters can be selected so the DCS implementation is both smaller and faster than the original implementation. However, DCS also introduces an overhead that is difficult for the designer to take into account, making it hard to determine whether a design is improved by DCS or not. This article presents extensive results on a profiling methodology that analyses Register-Transfer Level (RTL) implementations of applications to check if DCS would be beneficial. It proposes to use the functional density as a measure for the area efficiency of an implementation, as this measure contains both the overhead and the gains of a DCS implementation. The first step of the methodology is to analyse the dynamic behaviour of signals in the design, to find good parameter candidates. The overhead of DCS is highly dependent on this dynamic behaviour. A second stage calculates the functional density for each candidate and compares it to the functional density of the original design. The profiling methodology resulted in three implementations of a profiling tool, the DCS-RTL profiler. The execution time, accuracy, and the quality of each implementation is assessed based on data from 10 RTL designs. All designs, except for the two 16-bit adaptable Finite Impulse Response (FIR) filters, are analysed in 1 hour or less.},
  articleno    = {4},
  author       = {Davidson, Tom and Vansteenkiste, Elias and Heyse, Karel and Bruneel, Karel and Stroobandt, Dirk},
  issn         = {1936-7406},
  journal      = {ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS},
  language     = {eng},
  number       = {1},
  pages        = {24},
  title        = {Identification of dynamic circuit specialization opportunities in RTL code},
  url          = {http://dx.doi.org/10.1145/2629640},
  volume       = {8},
  year         = {2015},
}

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