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Parameterised FPGA reconfigurations for efficient test set generation

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Abstract
This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order to facilitate fault injection techniques. However, the development of previous FPGA fault injection techniques lacks efficiency, since they demonstrate either area or time overhead. This paper proposes a post-synthesis fault injection technique based on the single stuck-at fault concept, combining fault emulation with the parameterised configuration technique. The new fault-injected design is mapped with different mapping solutions based on dynamic specialisation of the logic and routing infrastructure of the FPGA during runtime. The experimental results for the proposed technique indicate a significant reduction of the logic depth and an area reduction up to a factor 10 compared to conventional tools.
Keywords
Parameterised Configurations, ATPG, FPGA, FAULT INJECTION, Fault Emulation, EMULATION, DESIGN

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Citation

Please use this url to cite or link to this publication:

MLA
Kourfali, Alexandra, Elias Vansteenkiste, and Dirk Stroobandt. “Parameterised FPGA Reconfigurations for Efficient Test Set Generation.” Proceedings International Conference on Reconfigurable Computing and FPGAs. 2014. Print.
APA
Kourfali, A., Vansteenkiste, E., & Stroobandt, D. (2014). Parameterised FPGA reconfigurations for efficient test set generation. Proceedings International Conference on Reconfigurable Computing and FPGAs. Presented at the 2014 International Conference on Reconfigurable Computing and FAGAs.
Chicago author-date
Kourfali, Alexandra, Elias Vansteenkiste, and Dirk Stroobandt. 2014. “Parameterised FPGA Reconfigurations for Efficient Test Set Generation.” In Proceedings International Conference on Reconfigurable Computing and FPGAs.
Chicago author-date (all authors)
Kourfali, Alexandra, Elias Vansteenkiste, and Dirk Stroobandt. 2014. “Parameterised FPGA Reconfigurations for Efficient Test Set Generation.” In Proceedings International Conference on Reconfigurable Computing and FPGAs.
Vancouver
1.
Kourfali A, Vansteenkiste E, Stroobandt D. Parameterised FPGA reconfigurations for efficient test set generation. Proceedings International Conference on Reconfigurable Computing and FPGAs. 2014.
IEEE
[1]
A. Kourfali, E. Vansteenkiste, and D. Stroobandt, “Parameterised FPGA reconfigurations for efficient test set generation,” in Proceedings International Conference on Reconfigurable Computing and FPGAs, Natl I Astrophysics Optics Elect (INAOE), Cancun, MEXICO, 2014.
@inproceedings{5836097,
  abstract     = {{This paper proposes the use of parameterised FPGA configurations for a new test set generation approach. The time-consuming problem of test set generation aims at finding the right input values to fully test an ASIC design. Since well-known methods for test set generation such as fault simulation techniques have become impractical to use due to their speed limitations, FPGAs have been used in order to facilitate fault injection techniques. However, the development of previous FPGA fault injection techniques lacks efficiency, since they demonstrate either area or time overhead. This paper proposes a post-synthesis fault injection technique based on the single stuck-at fault concept, combining fault emulation with the parameterised configuration technique. The new fault-injected design is mapped with different mapping solutions based on dynamic specialisation of the logic and routing infrastructure of the FPGA during runtime. The experimental results for the proposed technique indicate a significant reduction of the logic depth and an area reduction up to a factor 10 compared to conventional tools.}},
  author       = {{Kourfali, Alexandra and Vansteenkiste, Elias and Stroobandt, Dirk}},
  booktitle    = {{Proceedings International Conference on Reconfigurable Computing and FPGAs}},
  isbn         = {{978-1-4799-5944-0}},
  issn         = {{2325-6532}},
  keywords     = {{Parameterised Configurations,ATPG,FPGA,FAULT INJECTION,Fault Emulation,EMULATION,DESIGN}},
  language     = {{eng}},
  location     = {{Natl I Astrophysics Optics Elect (INAOE), Cancun, MEXICO}},
  pages        = {{6}},
  title        = {{Parameterised FPGA reconfigurations for efficient test set generation}},
  year         = {{2014}},
}

Web of Science
Times cited: