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Exploiting high-level synthesis tools for high-performance applications on FPGAs

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Abstract
Nowadays hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs) commonly replace multi-cores for high-performance applications. FPGAs are hardware accelerators that provide a programmable and massively parallel architecture, but the degree of freedom presents an additional challenge to create efficient designs in a short time span. While high-level synthesis (HLS) tools reduce the implementation effort, the huge design space exploration (DSE) demands a methodology to exploit the FPGA for a particular application in a reasonable time. In order to evaluate the efficiency of FPGAs, a roofline model was adapted to predict the performance and to quantify the impact of the HLS optimisations on the performance overhead. This model will be further fine-tuned and used to guide the design of selected algorithms for high performance execution.
Keywords
high level synthesis, FPGA, high performance, design space exploration

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Please use this url to cite or link to this publication:

Chicago
da Silva, Bruno, Erik D’Hollander, Dirk Stroobandt, and Abdellah Touhafi. 2014. “Exploiting High-level Synthesis Tools for High-performance Applications on FPGAs.” In 15th FEA Research Symposium Faculty of Engineering and Architecture, Abstracts, 28–28. Ghent, Belgium: UGent.
APA
da Silva, B., D’Hollander, E., Stroobandt, D., & Touhafi, A. (2014). Exploiting high-level synthesis tools for high-performance applications on FPGAs. 15th FEA research symposium Faculty of Engineering and Architecture, Abstracts (pp. 28–28). Presented at the 15th FEA research symposium Faculty of Engineering and Architecture, Ghent, Belgium: UGent.
Vancouver
1.
da Silva B, D’Hollander E, Stroobandt D, Touhafi A. Exploiting high-level synthesis tools for high-performance applications on FPGAs. 15th FEA research symposium Faculty of Engineering and Architecture, Abstracts. Ghent, Belgium: UGent; 2014. p. 28–28.
MLA
da Silva, Bruno, Erik D’Hollander, Dirk Stroobandt, et al. “Exploiting High-level Synthesis Tools for High-performance Applications on FPGAs.” 15th FEA Research Symposium Faculty of Engineering and Architecture, Abstracts. Ghent, Belgium: UGent, 2014. 28–28. Print.
@inproceedings{5831679,
  abstract     = {Nowadays hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs) commonly replace multi-cores for high-performance applications. FPGAs are hardware accelerators that provide a programmable and massively parallel architecture, but the degree of freedom presents an additional challenge to create efficient designs in a short time span. While high-level synthesis (HLS) tools reduce the implementation effort, the huge design space exploration (DSE) demands a methodology to exploit the FPGA for a particular application in a reasonable time. In order to evaluate the efficiency of FPGAs, a roofline model was adapted to predict the performance and to quantify the impact of the HLS optimisations on the performance overhead. This model will be further fine-tuned and used to guide the design of selected algorithms for high performance execution.},
  author       = {da Silva, Bruno and D'Hollander, Erik and Stroobandt, Dirk and Touhafi, Abdellah},
  booktitle    = {15th FEA research symposium Faculty of Engineering and Architecture, Abstracts},
  keyword      = {high level synthesis,FPGA,high performance,design space exploration},
  language     = {eng},
  location     = {Ghent, Belgium},
  pages        = {28--28},
  publisher    = {UGent},
  title        = {Exploiting high-level synthesis tools for high-performance applications on FPGAs},
  url          = {http://www.ugent.be/ea/nl/symposium.htm/boekje.pdf},
  year         = {2014},
}