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Mechanistic analytical modeling of superscalar in-order processor performance

Maximilien Breughe (UGent) , Stijn Eyerman (UGent) and Lieven Eeckhout (UGent)
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Abstract
Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application--microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application’s dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor. The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program--machine interactions, providing insight into microarchitecture bottlenecks; and (3) compiler--architecture interactions, visualizing the impact of compiler optimizations on performance.
Keywords
functional units, processor design space exploration, inter-instruction dependences, cycle stacks, Design, performance modeling, Experimentation, Superscalar in-order processors, Performance, Measurement, THROUGHPUT MODEL, SIMULATION, MICROPROCESSOR, PARALLELISM

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MLA
Breughe, Maximilien, et al. “Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance.” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, vol. 11, no. 4, 2015, doi:10.1145/2678277.
APA
Breughe, M., Eyerman, S., & Eeckhout, L. (2015). Mechanistic analytical modeling of superscalar in-order processor performance. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, 11(4). https://doi.org/10.1145/2678277
Chicago author-date
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. 2015. “Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance.” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 11 (4). https://doi.org/10.1145/2678277.
Chicago author-date (all authors)
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. 2015. “Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance.” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION 11 (4). doi:10.1145/2678277.
Vancouver
1.
Breughe M, Eyerman S, Eeckhout L. Mechanistic analytical modeling of superscalar in-order processor performance. ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION. 2015;11(4).
IEEE
[1]
M. Breughe, S. Eyerman, and L. Eeckhout, “Mechanistic analytical modeling of superscalar in-order processor performance,” ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, vol. 11, no. 4, 2015.
@article{5823684,
  abstract     = {{Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application--microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application’s dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor.

The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program--machine interactions, providing insight into microarchitecture bottlenecks; and (3) compiler--architecture interactions, visualizing the impact of compiler optimizations on performance.}},
  articleno    = {{50}},
  author       = {{Breughe, Maximilien and Eyerman, Stijn and Eeckhout, Lieven}},
  issn         = {{1544-3566}},
  journal      = {{ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION}},
  keywords     = {{functional units,processor design space exploration,inter-instruction dependences,cycle stacks,Design,performance modeling,Experimentation,Superscalar in-order processors,Performance,Measurement,THROUGHPUT MODEL,SIMULATION,MICROPROCESSOR,PARALLELISM}},
  language     = {{eng}},
  number       = {{4}},
  title        = {{Mechanistic analytical modeling of superscalar in-order processor performance}},
  url          = {{http://doi.org/10.1145/2678277}},
  volume       = {{11}},
  year         = {{2015}},
}

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