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The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism

Stijn Eyerman (UGent) and Lieven Eeckhout (UGent)
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Abstract
The number of active threads in a multi-core processor varies over time and is often much smaller than the number of supported hardware threads. This requires multi-core chip designs to balance core count and per-core performance. Low active thread counts benefit from a few big, high-performance cores, while high active thread counts benefit more from a sea of small, energy-efficient cores. This paper comprehensively studies the trade-offs in multi-core design given dynamically varying active thread counts. We find that, under these workload conditions, a homogeneous multi-core processor, consisting of a few high-performance SMT cores, typically outperforms heterogeneous multi-cores consisting of a mix of big and small cores (without SMT), within the same power budget. We also show that a homogeneous multi-core performs almost as well as a heterogeneous multi-core that also implements SMT, as well as a dynamic multi-core, while being less complex to design and verify. Further, heterogeneous multi-cores that power-gate idle cores yield (only) slightly better energy-efficiency compared to homogeneous multi-cores. The overall conclusion is that the benefit of SMT in the multi-core era is to provide flexibility with respect to the available thread-level parallelism. Consequently, homogeneous multi-cores with big SMT cores are competitive high-performance, energy-efficient design points for workloads with dynamically varying active thread counts.
Keywords
Single-ISA Heterogeneous Multi-Core, Thread-Level Parallelism, SMT, CHIP MULTIPROCESSOR, ARCHITECTURES, PERFORMANCE, AMDAHLS LAW, Chip Multi-Core Processor, PROCESSOR

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MLA
Eyerman, Stijn, and Lieven Eeckhout. “The Benefit of SMT in the Multi-core Era: Flexibility Towards Degrees of Thread-level Parallelism.” Proceedings of the 19th international conference on Architectural support for programming languages and operating systems 49.4 (2014): 591–606. Print.
APA
Eyerman, S., & Eeckhout, L. (2014). The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. Proceedings of the 19th international conference on Architectural support for programming languages and operating systems, 49(4), 591–606.
Chicago author-date
Eyerman, Stijn, and Lieven Eeckhout. 2014. “The Benefit of SMT in the Multi-core Era: Flexibility Towards Degrees of Thread-level Parallelism.” Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems 49 (4): 591–606.
Chicago author-date (all authors)
Eyerman, Stijn, and Lieven Eeckhout. 2014. “The Benefit of SMT in the Multi-core Era: Flexibility Towards Degrees of Thread-level Parallelism.” Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems 49 (4): 591–606.
Vancouver
1.
Eyerman S, Eeckhout L. The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism. Proceedings of the 19th international conference on Architectural support for programming languages and operating systems. 2014;49(4):591–606.
IEEE
[1]
S. Eyerman and L. Eeckhout, “The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism,” Proceedings of the 19th international conference on Architectural support for programming languages and operating systems, vol. 49, no. 4, pp. 591–606, 2014.
@article{5823631,
  abstract     = {The number of active threads in a multi-core processor varies over time and is often much smaller than the number of supported hardware threads. This requires multi-core chip designs to balance core count and per-core performance. Low active thread counts benefit from a few big, high-performance cores, while high active thread counts benefit more from a sea of small, energy-efficient cores.
This paper comprehensively studies the trade-offs in multi-core design given dynamically varying active thread counts. We find that, under these workload conditions, a homogeneous multi-core processor, consisting of a few high-performance SMT cores, typically outperforms heterogeneous multi-cores consisting of a mix of big and small cores (without SMT), within the same power budget. We also show that a homogeneous multi-core performs almost as well as a heterogeneous multi-core that also implements SMT, as well as a dynamic multi-core, while being less complex to design and verify. Further, heterogeneous multi-cores that power-gate idle cores yield (only) slightly better energy-efficiency compared to homogeneous multi-cores.
The overall conclusion is that the benefit of SMT in the multi-core era is to provide flexibility with respect to the available thread-level parallelism. Consequently, homogeneous multi-cores with big SMT cores are competitive high-performance, energy-efficient design points for workloads with dynamically varying active thread counts.},
  author       = {Eyerman, Stijn and Eeckhout, Lieven},
  issn         = {0362-1340},
  journal      = {Proceedings of the 19th international conference on Architectural support for programming languages and operating systems},
  keywords     = {Single-ISA Heterogeneous Multi-Core,Thread-Level Parallelism,SMT,CHIP MULTIPROCESSOR,ARCHITECTURES,PERFORMANCE,AMDAHLS LAW,Chip Multi-Core Processor,PROCESSOR},
  language     = {eng},
  number       = {4},
  pages        = {591--606},
  title        = {The benefit of SMT in the multi-core era: flexibility towards degrees of thread-level parallelism},
  url          = {http://dx.doi.org/10.1145/2541940.2541954},
  volume       = {49},
  year         = {2014},
}

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