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Center for nano- and biophotonics (NB-Photonics)
Abstract
Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes.. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm-STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of < 1% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as similar to 0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of >20 % from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to similar to 0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 % and high-quality (1.1x105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm-or standard 193nm-based patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.
Keywords
WDM devices, Silicon photonics, fiber-chip couplers, waveguides

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Chicago
Selvaraja, shankar kumar, Gustaf Winroth, Sabrina Locorotondo, Gayle Murdoch, Alexey Milenin, Christie Delvaux, Patrick Ong, et al. 2014. “193nm Immersion Lithography for High Performance Silicon Photonic Circuits.” In Proceedings of the Society of Photo-optical Instrumentation Engineers (spie), ed. K Lai and A Erdmann. Vol. 9052. SPIE.
APA
Selvaraja, shankar kumar, Winroth, G., Locorotondo, S., Murdoch, G., Milenin, A., Delvaux, C., Ong, P., et al. (2014). 193nm immersion lithography for high performance silicon photonic circuits. In K. Lai & A. Erdmann (Eds.), PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE) (Vol. 9052). Presented at the 27th Optical Microlithography Conference as part of the SPIE Advanced Lithography Symposium, SPIE.
Vancouver
1.
Selvaraja shankar kumar, Winroth G, Locorotondo S, Murdoch G, Milenin A, Delvaux C, et al. 193nm immersion lithography for high performance silicon photonic circuits. In: Lai K, Erdmann A, editors. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). SPIE; 2014.
MLA
Selvaraja, shankar kumar, Gustaf Winroth, Sabrina Locorotondo, et al. “193nm Immersion Lithography for High Performance Silicon Photonic Circuits.” Proceedings of the Society of Photo-optical Instrumentation Engineers (spie). Ed. K Lai & A Erdmann. Vol. 9052. SPIE, 2014. Print.
@inproceedings{5756363,
  abstract     = {Large-scale photonics integration has been proposed for many years to support the ever increasing requirements for long and short distance communications as well as package-to-package interconnects. Amongst the various technology options, silicon photonics has imposed itself as a promising candidate, relying on CMOS fabrication processes.. While silicon photonics can share the technology platform developed for advanced CMOS devices it has specific dimension control requirements. Though the device dimensions are in the order of the wavelength of light used, the tolerance allowed can be less than 1\% for certain devices. Achieving this is a challenging task which requires advanced patterning techniques along with process control. Another challenge is identifying an overlapping process window for diverse pattern densities and orientations on a single layer. In this paper, we present key technology challenges faced when using optical lithography for silicon photonics and advantages of using the 193nm immersion lithography system. We report successful demonstration of a modified 28nm-STI-like patterning platform for silicon photonics in 300mm Silicon-On-Insulator wafer technology. By careful process design, within-wafer CD variation (1sigma) of {\textlangle} 1\% is achieved for both isolated (waveguides) and dense (grating) patterns in silicon. In addition to dimensional control, low sidewall roughness is a crucial to achieve low scattering loss in the waveguides. With this platform, optical propagation loss as low as similar to 0.7 dB/cm is achieved for high-confinement single mode waveguides (450x220nm). This is an improvement of {\textrangle}20 \% from the best propagation loss reported for this cross-section fabricated using e-beam lithography. By using a single-mode low-confinement waveguide geometry the loss is further reduced to similar to 0.12 dB/cm. Secondly, we present improvement in within-device phase error in wavelength selective devices, a critical parameter which is a direct measure of line-width uniformity improvement due to the 193nm immersion system. In addition to these superior device performances, the platform opens scenarios for designing new device concepts using sub-wavelength features. By taking advantage of this, we demonstrate a cost-effective robust single-etch sub-wavelength structure based fiber-chip coupler with a coupling efficiency of 40 \% and high-quality (1.1x105) factor wavelength filters. These demonstrations on the 193nm immersion lithography show superior performance both in terms of dimensional uniformity and device functionality compared to 248nm-or standard 193nm-based patterning in high-volume manufacture platform. Furthermore, using the wafer and patterning technology similar to advanced CMOS technology brings silicon photonics closer toward an integrated optical interconnect.},
  articleno    = {90520F},
  author       = {Selvaraja, shankar kumar and Winroth, Gustaf and Locorotondo, Sabrina and Murdoch, Gayle and Milenin, Alexey and Delvaux, Christie and Ong, Patrick and Pathak, Shibnath and Xie, Weiqiang and Sterckx, Gunther and Lepage, Guy and Van Thourhout, Dries and Bogaerts, Wim and Van Campenhout, Joris and Absil, Philippe},
  booktitle    = {PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)},
  editor       = {Lai, K and Erdmann, A },
  isbn         = {9780819499752},
  issn         = {0277-786X},
  language     = {eng},
  location     = {San Jose, CA, USA},
  pages        = {9},
  publisher    = {SPIE},
  title        = {193nm immersion lithography for high performance silicon photonic circuits},
  url          = {http://dx.doi.org/10.1117/12.2049004},
  volume       = {9052},
  year         = {2014},
}

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