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Epoch profiles: microarchitecture-based application analysis and optimization

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Abstract
The performance of data-intensive applications, when running on modern multi- and many-core processors, is largely determined by their memory access behavior. Its most important contributors are the frequency and latency of off-chip accesses and the extent to which long-latency memory accesses can be overlapped with useful computation or with each other. In this paper we present two methods to better understand application and microarchitectural interactions. An epoch profile is an intuitive way to understand the relationships between three important characteristics: the on-chip cache size, the size of the reorder window of an out-of-order processor, and the frequency of processor stalls caused by long-latency, off-chip requests (epochs). By relating these three quantities one can more easily understand an application’s memory reference behavior and thus significantly reduce the design space. While epoch profiles help to provide insight into the behavior of a single application, developing an understanding of a number of applications in the presence of area and core count constraints presents additional challenges. Epoch-based microarchitectural analysis is presented as a better way to understand the trade-offs for memory-bound applications in the presence of these physical constraints. Through epoch profiling and optimization, one can significantly reduce the multidimensional design space for hardware/software optimization through the use of high-level model-driven techniques.
Keywords
memory-level parallelism, Microarchitecture analysis, visualization

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MLA
Carlson, Trevor, et al. “Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 14, no. 1, 2015, pp. 30–33, doi:10.1109/LCA.2014.2329873.
APA
Carlson, T., Nilakantan, S., Hempstead, M., & Heirman, W. (2015). Epoch profiles: microarchitecture-based application analysis and optimization. IEEE COMPUTER ARCHITECTURE LETTERS, 14(1), 30–33. https://doi.org/10.1109/LCA.2014.2329873
Chicago author-date
Carlson, Trevor, Siddharth Nilakantan, Mark Hempstead, and Wim Heirman. 2015. “Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.” IEEE COMPUTER ARCHITECTURE LETTERS 14 (1): 30–33. https://doi.org/10.1109/LCA.2014.2329873.
Chicago author-date (all authors)
Carlson, Trevor, Siddharth Nilakantan, Mark Hempstead, and Wim Heirman. 2015. “Epoch Profiles: Microarchitecture-Based Application Analysis and Optimization.” IEEE COMPUTER ARCHITECTURE LETTERS 14 (1): 30–33. doi:10.1109/LCA.2014.2329873.
Vancouver
1.
Carlson T, Nilakantan S, Hempstead M, Heirman W. Epoch profiles: microarchitecture-based application analysis and optimization. IEEE COMPUTER ARCHITECTURE LETTERS. 2015;14(1):30–3.
IEEE
[1]
T. Carlson, S. Nilakantan, M. Hempstead, and W. Heirman, “Epoch profiles: microarchitecture-based application analysis and optimization,” IEEE COMPUTER ARCHITECTURE LETTERS, vol. 14, no. 1, pp. 30–33, 2015.
@article{5687291,
  abstract     = {{The performance of data-intensive applications, when running on modern multi- and many-core processors, is largely determined by their memory access behavior. Its most important contributors are the frequency and latency of off-chip accesses and the extent to which long-latency memory accesses can be overlapped with useful computation or with each other.
In this paper we present two methods to better understand application and microarchitectural interactions. An epoch profile is an intuitive way to understand the relationships between three important characteristics: the on-chip cache size, the size of the reorder window of an out-of-order processor, and the frequency of processor stalls caused by long-latency, off-chip requests (epochs). By relating these three quantities one can more easily understand an application’s memory reference behavior and thus significantly reduce the design space. While epoch profiles help to provide insight into the behavior of a single application, developing an understanding of a number of applications in the presence of area and core count constraints presents additional challenges. Epoch-based microarchitectural analysis is presented as a better way to understand the trade-offs for memory-bound applications in the presence of these physical constraints.
Through epoch profiling and optimization, one can significantly reduce the multidimensional design space for hardware/software optimization through the use of high-level model-driven techniques.}},
  author       = {{Carlson, Trevor and Nilakantan, Siddharth and Hempstead, Mark and Heirman, Wim}},
  issn         = {{1556-6056}},
  journal      = {{IEEE COMPUTER ARCHITECTURE LETTERS}},
  keywords     = {{memory-level parallelism,Microarchitecture analysis,visualization}},
  language     = {{eng}},
  number       = {{1}},
  pages        = {{30--33}},
  title        = {{Epoch profiles: microarchitecture-based application analysis and optimization}},
  url          = {{http://doi.org/10.1109/LCA.2014.2329873}},
  volume       = {{14}},
  year         = {{2015}},
}

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