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Comparing and combining GPU and FPGA accelerators in an image processing context

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Abstract
Nowadays, processors alone cannot deliver what computation hungry image processing applications demand. An alternative is to use hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs). Applications, however, exhibit different performance characteristics depending on the accelerator. This paper describes the hybrid platform and the programming environment that allows to efficiently create programs on a combined GPU/FPGA desktop. We use the roofline model to identify the most appropriate accelerator for each application and High-Level Synthesis (HLS) tools to reduce the FPGA development time. To introduce our platform and tool chain both accelerators are compared by implementing a basic image operation. Next, a promising algorithm is explored and implemented, splitting and distributing the work between GPU, FPGA and CPU in order to validate the hybrid concept. Our results show that their combination exhibits a higher performance for computational intensive image processing applications than a GPU only.
Keywords
graphics processing units, FPGA, High-level syntehsis, Roofline model, field programmable gate arrays, GPU, high performance computing

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Chicago
da Silva, Bruno, An Braeken, Erik D’Hollander, Abdellah Touhafi, Jan Cornelis, and Jan Lemeire. 2013. “Comparing and Combining GPU and FPGA Accelerators in an Image Processing Context.” In International Conference on Field Programmable and Logic Applications, ed. João MP Cardoso, Katherine Morrow, and Pedro C Diniz. New York, NY, USA: IEEE.
APA
da Silva, B., Braeken, A., D’Hollander, E., Touhafi, A., Cornelis, J., & Lemeire, J. (2013). Comparing and combining GPU and FPGA accelerators in an image processing context. In J. M. Cardoso, K. Morrow, & P. C. Diniz (Eds.), International Conference on Field Programmable and Logic Applications. Presented at the 23rd International conference on Field Programmable Logic and Applications (FPL 2013), New York, NY, USA: IEEE.
Vancouver
1.
da Silva B, Braeken A, D’Hollander E, Touhafi A, Cornelis J, Lemeire J. Comparing and combining GPU and FPGA accelerators in an image processing context. In: Cardoso JM, Morrow K, Diniz PC, editors. International Conference on Field Programmable and Logic Applications. New York, NY, USA: IEEE; 2013.
MLA
da Silva, Bruno, An Braeken, Erik D’Hollander, et al. “Comparing and Combining GPU and FPGA Accelerators in an Image Processing Context.” International Conference on Field Programmable and Logic Applications. Ed. João MP Cardoso, Katherine Morrow, & Pedro C Diniz. New York, NY, USA: IEEE, 2013. Print.
@inproceedings{4406930,
  abstract     = {Nowadays, processors alone cannot deliver what computation hungry image processing applications demand. An alternative is to use hardware accelerators such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs). Applications, however, exhibit different performance characteristics depending on the accelerator. This paper describes the hybrid platform and the programming environment that allows to efficiently create programs on a combined GPU/FPGA desktop. We use the roofline model to identify the most appropriate accelerator for each application and High-Level Synthesis (HLS) tools to reduce the FPGA development time. To introduce our platform and tool chain both accelerators are compared by implementing a basic image operation. Next, a promising algorithm is explored and implemented, splitting and distributing the work between GPU, FPGA and CPU in order to validate the hybrid concept. Our results show that their combination exhibits a higher performance for computational intensive image processing applications than a GPU only.},
  author       = {da Silva, Bruno and Braeken, An and D'Hollander, Erik and Touhafi, Abdellah and Cornelis, Jan and Lemeire, Jan},
  booktitle    = {International Conference on Field Programmable and Logic Applications},
  editor       = {Cardoso, Jo{\~a}o MP and Morrow, Katherine and Diniz, Pedro C},
  isbn         = {9781479900046},
  issn         = {1946-1488},
  keyword      = {graphics processing units,FPGA,High-level syntehsis,Roofline model,field programmable gate arrays,GPU,high performance computing},
  language     = {eng},
  location     = {Porto, Portugal},
  pages        = {4},
  publisher    = {IEEE},
  title        = {Comparing and combining GPU and FPGA accelerators in an image processing context},
  url          = {http://dx.doi.org/10.1109/FPL.2013.6645552},
  year         = {2013},
}

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