On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA's configuration infrastructure
- Author
- Karel Heyse, Dirk Stroobandt (UGent) , Oliver Kadlcek and Oliver Pell
- Organization
- Abstract
- It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used. A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.
- Keywords
- HPC, block RAM, partial reconfiguration, FPGA
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-4366600
- MLA
- Heyse, Karel, et al. “On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure.” Reconfigurable Computing : Architectures, Tools, and Applications, 10th International Symposium, ARC 2014, Proceedings, edited by Diana Goehringer et al., vol. 8405, Springer, 2014, pp. 85–96, doi:10.1007/978-3-319-05960-0_8.
- APA
- Heyse, K., Stroobandt, D., Kadlcek, O., & Pell, O. (2014). On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA’s configuration infrastructure. In D. Goehringer, M. D. Santambrogio, J. M. P. Cardoso, & K. Bertels (Eds.), Reconfigurable computing : architectures, tools, and applications, 10th International Symposium, ARC 2014, Proceedings (Vol. 8405, pp. 85–96). https://doi.org/10.1007/978-3-319-05960-0_8
- Chicago author-date
- Heyse, Karel, Dirk Stroobandt, Oliver Kadlcek, and Oliver Pell. 2014. “On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure.” In Reconfigurable Computing : Architectures, Tools, and Applications, 10th International Symposium, ARC 2014, Proceedings, edited by Diana Goehringer, Marco Domenico Santambrogio, João M. P. Cardoso, and Koen Bertels, 8405:85–96. Springer. https://doi.org/10.1007/978-3-319-05960-0_8.
- Chicago author-date (all authors)
- Heyse, Karel, Dirk Stroobandt, Oliver Kadlcek, and Oliver Pell. 2014. “On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure.” In Reconfigurable Computing : Architectures, Tools, and Applications, 10th International Symposium, ARC 2014, Proceedings, ed by. Diana Goehringer, Marco Domenico Santambrogio, João M. P. Cardoso, and Koen Bertels, 8405:85–96. Springer. doi:10.1007/978-3-319-05960-0_8.
- Vancouver
- 1.Heyse K, Stroobandt D, Kadlcek O, Pell O. On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA’s configuration infrastructure. In: Goehringer D, Santambrogio MD, Cardoso JMP, Bertels K, editors. Reconfigurable computing : architectures, tools, and applications, 10th International Symposium, ARC 2014, Proceedings. Springer; 2014. p. 85–96.
- IEEE
- [1]K. Heyse, D. Stroobandt, O. Kadlcek, and O. Pell, “On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA’s configuration infrastructure,” in Reconfigurable computing : architectures, tools, and applications, 10th International Symposium, ARC 2014, Proceedings, Vilamoura, Portugal, 2014, vol. 8405, pp. 85–96.
@inproceedings{4366600,
abstract = {{It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used. A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.}},
author = {{Heyse, Karel and Stroobandt, Dirk and Kadlcek, Oliver and Pell, Oliver}},
booktitle = {{Reconfigurable computing : architectures, tools, and applications, 10th International Symposium, ARC 2014, Proceedings}},
editor = {{Goehringer, Diana and Santambrogio, Marco Domenico and Cardoso, João M. P. and Bertels, Koen}},
isbn = {{9783319059594}},
issn = {{0302-9743}},
keywords = {{HPC,block RAM,partial reconfiguration,FPGA}},
language = {{eng}},
location = {{Vilamoura, Portugal}},
pages = {{85--96}},
publisher = {{Springer}},
title = {{On the impact of replacing a low-speed memory bus on the Maxeler platform, using the FPGA's configuration infrastructure}},
url = {{http://doi.org/10.1007/978-3-319-05960-0_8}},
volume = {{8405}},
year = {{2014}},
}
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