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StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs

Brahim Al Farisi (UGent) , Karel Bruneel (UGent) and Dirk Stroobandt (UGent)
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Abstract
Using Dynamic Partial Reconfiguration (DPR) of FPGAs, several circuits can be time-multiplexed on the same chip region, saving considerable area. However, the long reconfiguration time when switching between circuits remains a large problem with DPR. In this paper we show it is possible to significantly reduce reconfiguration time when the number of circuits is limited. We tackle the problem by reducing the time needed to reconfigure the FPGA's routing. We divide the configuration memory of the FPGA's routing in a static and a dynamic portion. A novel router, called StaticRoute, is presented that is able to route the nets of the different circuits in such a way that the static portion is shared and only the dynamic portion needs to be reconfigured. The static portion of the configuration memory does not need to be rewritten during run-time. In the experiments we show it is possible to reach a 2× speed-up of the reconfiguration process, while the increase in wire length per circuit is limited.
Keywords
dynamic partial reconfiguration, FPGA, Field programmable gate arrays

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Chicago
Al Farisi, Brahim, Karel Bruneel, and Dirk Stroobandt. 2013. “StaticRoute: a Novel Router for the Dynamic Partial Reconfiguration of FPGAs.” In International Conference on Field Programmable and Logic Applications, ed. João MP Cardoso, Katherina Morrow, and Pedro C Diniz. New York, NY, USA: IEEE.
APA
Al Farisi, B., Bruneel, K., & Stroobandt, D. (2013). StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs. In J. M. Cardoso, K. Morrow, & P. C. Diniz (Eds.), International Conference on Field Programmable and Logic Applications. Presented at the 23rd International conference on Field Programmable Logic and Applications (FPL 2013), New York, NY, USA: IEEE.
Vancouver
1.
Al Farisi B, Bruneel K, Stroobandt D. StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs. In: Cardoso JM, Morrow K, Diniz PC, editors. International Conference on Field Programmable and Logic Applications. New York, NY, USA: IEEE; 2013.
MLA
Al Farisi, Brahim, Karel Bruneel, and Dirk Stroobandt. “StaticRoute: a Novel Router for the Dynamic Partial Reconfiguration of FPGAs.” International Conference on Field Programmable and Logic Applications. Ed. João MP Cardoso, Katherina Morrow, & Pedro C Diniz. New York, NY, USA: IEEE, 2013. Print.
@inproceedings{4326112,
  abstract     = {Using Dynamic Partial Reconfiguration (DPR) of FPGAs, several circuits can be time-multiplexed on the same chip region, saving considerable area. However, the long reconfiguration time when switching between circuits remains a large problem with DPR. In this paper we show it is possible to significantly reduce reconfiguration time when the number of circuits is limited. We tackle the problem by reducing the time needed to reconfigure the FPGA's routing. We divide the configuration memory of the FPGA's routing in a static and a dynamic portion. A novel router, called StaticRoute, is presented that is able to route the nets of the different circuits in such a way that the static portion is shared and only the dynamic portion needs to be reconfigured. The static portion of the configuration memory does not need to be rewritten during run-time. In the experiments we show it is possible to reach a 2{\texttimes} speed-up of the reconfiguration process, while the increase in wire length per circuit is limited.},
  author       = {Al Farisi, Brahim and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {International Conference on Field Programmable and Logic Applications},
  editor       = {Cardoso, Jo{\~a}o MP and Morrow, Katherina and Diniz, Pedro C},
  isbn         = {9781479900046},
  issn         = {1946-1488},
  language     = {eng},
  location     = {Porto, Portugal},
  pages        = {7},
  publisher    = {IEEE},
  title        = {StaticRoute: a novel router for the dynamic partial reconfiguration of FPGAs},
  url          = {http://dx.doi.org/10.1109/FPL.2013.6645512},
  year         = {2013},
}

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