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Project
  • EU FP7 project FASTER
Abstract
Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. software component adaptivity is straightforward but not enough: recent products include hardware accelerators for reasons of performance and power efficiency that also need to adapt to new requirements. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. For the Intrusion Detection System example, new rules can be hardcoded into the reconfigurable logic, achieving high performance, while providing the necessary adaptivity to new threats. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform combining a general purpose processor with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design- and run-time, the capabilities of partial dynamic reconfiguration. The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology.
Keywords
FPGA, dynamic reconfiguration

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Citation

Please use this url to cite or link to this publication:

MLA
Santambrogio, Marco D et al. “The FASTER Vision for Designing Dynamically Reconfigurable Systems.” International Conference on IC Design and Technology, Proceedings. 2013. 1–4. Print.
APA
Santambrogio, M. D., Pilato, C., Pnevmatikatos, D., Papadimitriou, K., Stroobandt, D., & Sciuto, D. (2013). The FASTER vision for designing dynamically reconfigurable systems. International Conference on IC Design and Technology, Proceedings (pp. 1–4). Presented at the International Conference on IC Design and Technology (ICICDT - 2013).
Chicago author-date
Santambrogio, Marco D, Christiano Pilato, Dionisios Pnevmatikatos, Kyprianos Papadimitriou, Dirk Stroobandt, and Donatella Sciuto. 2013. “The FASTER Vision for Designing Dynamically Reconfigurable Systems.” In International Conference on IC Design and Technology, Proceedings, 1–4.
Chicago author-date (all authors)
Santambrogio, Marco D, Christiano Pilato, Dionisios Pnevmatikatos, Kyprianos Papadimitriou, Dirk Stroobandt, and Donatella Sciuto. 2013. “The FASTER Vision for Designing Dynamically Reconfigurable Systems.” In International Conference on IC Design and Technology, Proceedings, 1–4.
Vancouver
1.
Santambrogio MD, Pilato C, Pnevmatikatos D, Papadimitriou K, Stroobandt D, Sciuto D. The FASTER vision for designing dynamically reconfigurable systems. International Conference on IC Design and Technology, Proceedings. 2013. p. 1–4.
IEEE
[1]
M. D. Santambrogio, C. Pilato, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt, and D. Sciuto, “The FASTER vision for designing dynamically reconfigurable systems,” in International Conference on IC Design and Technology, Proceedings, Pavia, Italy, 2013, pp. 1–4.
@inproceedings{4252387,
  abstract     = {Extending product functionality and lifetime requires constant addition of new features to satisfy the growing customer needs and the evolving market and technology trends. software component adaptivity is straightforward but not enough: recent products include hardware accelerators for reasons of performance and power efficiency that also need to adapt to new requirements. Reconfigurable logic allows the definition of new functions to be implemented in dynamically instantiated hardware units, combining adaptivity with hardware speed and efficiency. For the Intrusion Detection System example, new rules can be hardcoded into the reconfigurable logic, achieving high performance, while providing the necessary adaptivity to new threats. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform combining a general purpose processor with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design- and run-time, the capabilities of partial dynamic reconfiguration. The FASTER project will facilitate the use of reconfigurable hardware by providing a complete methodology that enables designers to easily implement and verify applications on platforms with general-purpose processors and acceleration modules implemented in the latest reconfigurable technology.},
  author       = {Santambrogio, Marco D and Pilato, Christiano and Pnevmatikatos, Dionisios and Papadimitriou, Kyprianos and Stroobandt, Dirk and Sciuto, Donatella},
  booktitle    = {International Conference on IC Design and Technology, Proceedings},
  isbn         = {9781467347419},
  keywords     = {FPGA,dynamic reconfiguration},
  language     = {eng},
  location     = {Pavia, Italy},
  pages        = {1--4},
  title        = {The FASTER vision for designing dynamically reconfigurable systems},
  year         = {2013},
}