Advanced search
1 file | 1.69 MB Add to list
Author
Organization
Project
  • EU FP7 project FASTER
Abstract
Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.
Keywords
dynamic reconfiguration, FPGA

Downloads

  • ALL-ReCoSoC2012.pdf
    • full text
    • |
    • open access
    • |
    • PDF
    • |
    • 1.69 MB

Citation

Please use this url to cite or link to this publication:

MLA
Santambrogio, Marco D et al. “Smart Technologies for Effective Reconfiguration: The FASTER Approach.” 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC). Ed. LS Indrusiak, G Gogniat, & N Voros. IEEE, 2012. 1–7. Print.
APA
Santambrogio, M. D., Pnevmatikatos, D., Papadimitriou, K., Pilato, C., Gaydadjiev, G., Stroobandt, D., Davidson, T., et al. (2012). Smart technologies for effective reconfiguration: the FASTER approach. In L. Indrusiak, G. Gogniat, & N. Voros (Eds.), 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC) (pp. 1–7). Presented at the 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), IEEE.
Chicago author-date
Santambrogio, Marco D, Dionisios Pnevmatikatos, Kyprianos Papadimitriou, Christiano Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, et al. 2012. “Smart Technologies for Effective Reconfiguration: The FASTER Approach.” In 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), ed. LS Indrusiak, G Gogniat, and N Voros, 1–7. IEEE.
Chicago author-date (all authors)
Santambrogio, Marco D, Dionisios Pnevmatikatos, Kyprianos Papadimitriou, Christiano Pilato, Georgi Gaydadjiev, Dirk Stroobandt, Tom Davidson, Tobias Becker, Tim Todman, Wayne Luk, A Bonetto, A Cazzaniga, GC Durelli, and Donatella Sciuto. 2012. “Smart Technologies for Effective Reconfiguration: The FASTER Approach.” In 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), ed. LS Indrusiak, G Gogniat, and N Voros, 1–7. IEEE.
Vancouver
1.
Santambrogio MD, Pnevmatikatos D, Papadimitriou K, Pilato C, Gaydadjiev G, Stroobandt D, et al. Smart technologies for effective reconfiguration: the FASTER approach. In: Indrusiak L, Gogniat G, Voros N, editors. 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC). IEEE; 2012. p. 1–7.
IEEE
[1]
M. D. Santambrogio et al., “Smart technologies for effective reconfiguration: the FASTER approach,” in 2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), York, England, 2012, pp. 1–7.
@inproceedings{4252244,
  abstract     = {Current and future computing systems increasingly require that their functionality stays flexible after the system is operational, in order to cope with changing user requirements and improvements in system features, i.e. changing protocols and data-coding standards, evolving demands for support of different user applications, and newly emerging applications in communication, computing and consumer electronics. Therefore, extending the functionality and the lifetime of products requires the addition of new functionality to track and satisfy the customers needs and market and technology trends. Many contemporary products along with the software part incorporate hardware accelerators for reasons of performance and power efficiency. While adaptivity of software is straightforward, adaptation of the hardware to changing requirements constitutes a challenging problem requiring delicate solutions. The FASTER (Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration) project aims at introducing a complete methodology to allow designers to easily implement a system specification on a platform which includes a general purpose processor combined with multiple accelerators running on an FPGA, taking as input a high-level description and fully exploiting, both at design time and at run time, the capabilities of partial dynamic reconfiguration. The goal is that for selected application domains, the FASTER toolchain will be able to reduce the design and verification time of complex reconfigurable systems providing additional novel verification features that are not available in existing tool flows.},
  author       = {Santambrogio, Marco D and Pnevmatikatos, Dionisios and Papadimitriou, Kyprianos and Pilato, Christiano and Gaydadjiev, Georgi and Stroobandt, Dirk and Davidson, Tom and Becker, Tobias and Todman, Tim and Luk, Wayne and Bonetto, A and Cazzaniga, A and Durelli, GC and Sciuto, Donatella},
  booktitle    = {2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC)},
  editor       = {Indrusiak, LS and Gogniat, G and Voros, N},
  isbn         = {9781467325721},
  keywords     = {dynamic reconfiguration,FPGA},
  language     = {eng},
  location     = {York, England},
  pages        = {1--7},
  publisher    = {IEEE},
  title        = {Smart technologies for effective reconfiguration: the FASTER approach},
  year         = {2012},
}

Web of Science
Times cited: