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A stochastic model for the interconnection topology of digital circuits

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MLA
Verplaetse, Peter, et al. “A Stochastic Model for the Interconnection Topology of Digital Circuits.” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 9, no. 6, 2001, pp. 938–42.
APA
Verplaetse, P., Stroobandt, D., & Van Campenhout, J. (2001). A stochastic model for the interconnection topology of digital circuits. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 9(6), 938–942.
Chicago author-date
Verplaetse, Peter, Dirk Stroobandt, and Jan Van Campenhout. 2001. “A Stochastic Model for the Interconnection Topology of Digital Circuits.” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 9 (6): 938–42.
Chicago author-date (all authors)
Verplaetse, Peter, Dirk Stroobandt, and Jan Van Campenhout. 2001. “A Stochastic Model for the Interconnection Topology of Digital Circuits.” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 9 (6): 938–942.
Vancouver
1.
Verplaetse P, Stroobandt D, Van Campenhout J. A stochastic model for the interconnection topology of digital circuits. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS. 2001;9(6):938–42.
IEEE
[1]
P. Verplaetse, D. Stroobandt, and J. Van Campenhout, “A stochastic model for the interconnection topology of digital circuits,” IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, vol. 9, no. 6, pp. 938–942, 2001.
@article{420049,
  author       = {{Verplaetse, Peter and Stroobandt, Dirk and Van Campenhout, Jan}},
  issn         = {{1063-8210}},
  journal      = {{IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS}},
  language     = {{eng}},
  number       = {{6}},
  pages        = {{938--942}},
  title        = {{A stochastic model for the interconnection topology of digital circuits}},
  volume       = {{9}},
  year         = {{2001}},
}

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Times cited: