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Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS

Karel Heyse (UGent) , Tom Davidson (UGent) , Elias Vansteenkiste (UGent) , Karel Bruneel (UGent) and Dirk Stroobandt (UGent)
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Abstract
Fine grained Field Programmable Gate Arrays (FPGA) are complex to program and therefore suffer from high development costs. To solve this problem, Virtual Coarse Grained Reconfigurable Arrays (Virtual CGRA), or CGRAs implemented on FPGAs, have been proposed. Conventional implementations of VCGRAs use functional FPGA resources, such as LookUp Tables, to implement the virtual switch blocks, registers and other components that make the VCGRA configurable. We show that this is a large overhead that can often be avoided by mapping these components directly on lower level FPGA resources such as physical switch blocks and configuration memory. We show how this can be achieved using the tool flow for parameterised FPGA configurations and illustrate the advantages of this method by showing that an area reduction of 50% is attainable for a VCGRA aimed at regular expression matching.
Keywords
field programmable gate arrays, virtual coarse grained reconfigurable arrays, reconfigurable architectures

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MLA
Heyse, Karel, et al. “Efficient Implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.” International Conference on Field Programmable and Logic Applications, edited by JMP Cardoso et al., IEEE, 2013, pp. 1–8.
APA
Heyse, K., Davidson, T., Vansteenkiste, E., Bruneel, K., & Stroobandt, D. (2013). Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS. In J. Cardoso, K. Morrow, & P. Diniz (Eds.), International Conference on Field Programmable and Logic Applications (pp. 1–8). Piscataway, NJ, USA: IEEE.
Chicago author-date
Heyse, Karel, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, and Dirk Stroobandt. 2013. “Efficient Implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.” In International Conference on Field Programmable and Logic Applications, edited by JMP Cardoso, K Morrow, and PC Diniz, 1–8. Piscataway, NJ, USA: IEEE.
Chicago author-date (all authors)
Heyse, Karel, Tom Davidson, Elias Vansteenkiste, Karel Bruneel, and Dirk Stroobandt. 2013. “Efficient Implementation of Virtual Coarse Grained Reconfigurable Arrays on FPGAS.” In International Conference on Field Programmable and Logic Applications, ed by. JMP Cardoso, K Morrow, and PC Diniz, 1–8. Piscataway, NJ, USA: IEEE.
Vancouver
1.
Heyse K, Davidson T, Vansteenkiste E, Bruneel K, Stroobandt D. Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS. In: Cardoso J, Morrow K, Diniz P, editors. International Conference on Field Programmable and Logic Applications. Piscataway, NJ, USA: IEEE; 2013. p. 1–8.
IEEE
[1]
K. Heyse, T. Davidson, E. Vansteenkiste, K. Bruneel, and D. Stroobandt, “Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS,” in International Conference on Field Programmable and Logic Applications, Porto, Portugal, 2013, pp. 1–8.
@inproceedings{4199215,
  abstract     = {Fine grained Field Programmable Gate Arrays (FPGA) are complex to program and therefore suffer from high development costs. To solve this problem, Virtual Coarse Grained Reconfigurable Arrays (Virtual CGRA), or CGRAs implemented on FPGAs, have been proposed. Conventional implementations of VCGRAs use functional FPGA resources, such as LookUp Tables, to implement the virtual switch blocks, registers and other components that make the VCGRA configurable. We show that this is a large overhead that can often be avoided by mapping these components directly on lower level FPGA resources such as physical switch blocks and configuration memory. We show how this can be achieved using the tool flow for parameterised FPGA configurations and illustrate the advantages of this method by showing that an area reduction of 50% is attainable for a VCGRA aimed at regular expression matching.},
  author       = {Heyse, Karel and Davidson, Tom and Vansteenkiste, Elias and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {International Conference on Field Programmable and Logic Applications},
  editor       = {Cardoso, JMP and Morrow, K and Diniz, PC},
  isbn         = {9781479900046},
  issn         = {1946-1488},
  keywords     = {field programmable gate arrays,virtual coarse grained reconfigurable arrays,reconfigurable architectures},
  language     = {eng},
  location     = {Porto, Portugal},
  pages        = {1--8},
  publisher    = {IEEE},
  title        = {Efficient implementation of virtual coarse grained reconfigurable arrays on FPGAS},
  url          = {http://dx.doi.org/10.1109/FPL.2013.6645516},
  year         = {2013},
}

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