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Finding and applying loop transformations for generating optimized FPGA implementations

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Abstract
When implementing multimedia applications, solutions in dedicated hardware are chosen only when the required performance or energy-efficiency cannot be met with a software solution. The performance of a hardware design critically depends upon having high levels of parallelism and data locality. Often a long sequence of high-level transformations is needed to sufficiently increase the locality and parallelism. The effect of the transformations is known only after translating the high-level code into a specific design at the circuit level. When the constraints are not met, hardware designers need to redo the high-level loop transformations, and repeat all subsequent translation steps, which leads to long design times. We propose a method to reduce design time through the synergistic combination of techniques (a) to quickly pinpoint the loop transformations that increase locality; (b) to refactor loops in a polyhedral model and check whether a sequence of refactorings is legal; (c) to generate efficient structural VHDL from the optimized refactored algorithm. The implementation of these techniques in a tool suite results in a far shorter design time of hours instead of days or weeks. A 2D-inverse discrete wavelet transform was taken as a case study. The results outperform those of a commercial C-to-VHDL compiler, and compare favorably with existing published approaches.
Keywords
IMPROVING DATA LOCALITY, WAVELET TRANSFORM, ARCHITECTURE, DESIGN

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Chicago
Devos, Harald, Kristof Beyls, Mark Christiaens, Jan Van Campenhout, Erik D’Hollander, and Dirk Stroobandt. 2007. “Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.” In Lecture Notes in Computer Science, ed. P Stenstrom, M O’Boyle, F Bodin, M Cintra, and SA McKee, 4050:159–178. Berlin, Germany: Springer.
APA
Devos, Harald, Beyls, K., Christiaens, M., Van Campenhout, J., D’Hollander, E., & Stroobandt, D. (2007). Finding and applying loop transformations for generating optimized FPGA implementations. In P. Stenstrom, M. O’Boyle, F. Bodin, M. Cintra, & S. McKee (Eds.), LECTURE NOTES IN COMPUTER SCIENCE (Vol. 4050, pp. 159–178). Presented at the 1st International conference on High-Performance Embedded Architectures and Compilers, Berlin, Germany: Springer.
Vancouver
1.
Devos H, Beyls K, Christiaens M, Van Campenhout J, D’Hollander E, Stroobandt D. Finding and applying loop transformations for generating optimized FPGA implementations. In: Stenstrom P, O’Boyle M, Bodin F, Cintra M, McKee S, editors. LECTURE NOTES IN COMPUTER SCIENCE. Berlin, Germany: Springer; 2007. p. 159–78.
MLA
Devos, Harald, Kristof Beyls, Mark Christiaens, et al. “Finding and Applying Loop Transformations for Generating Optimized FPGA Implementations.” Lecture Notes in Computer Science. Ed. P Stenstrom et al. Vol. 4050. Berlin, Germany: Springer, 2007. 159–178. Print.
@inproceedings{419730,
  abstract     = {When implementing multimedia applications, solutions in dedicated hardware are chosen only when the required performance or energy-efficiency cannot be met with a software solution. The performance of a hardware design critically depends upon having high levels of parallelism and data locality. Often a long sequence of high-level transformations is needed to sufficiently increase the locality and parallelism. The effect of the transformations is known only after translating the high-level code into a specific design at the circuit level. When the constraints are not met, hardware designers need to redo the high-level loop transformations, and repeat all subsequent translation steps, which leads to long design times.
We propose a method to reduce design time through the synergistic combination of techniques (a) to quickly pinpoint the loop transformations that increase locality; (b) to refactor loops in a polyhedral model and check whether a sequence of refactorings is legal; (c) to generate efficient structural VHDL from the optimized refactored algorithm.
The implementation of these techniques in a tool suite results in a far shorter design time of hours instead of days or weeks. A 2D-inverse discrete wavelet transform was taken as a case study. The results outperform those of a commercial C-to-VHDL compiler, and compare favorably with existing published approaches.},
  author       = {Devos, Harald and Beyls, Kristof and Christiaens, Mark and Van Campenhout, Jan and D'Hollander, Erik and Stroobandt, Dirk},
  booktitle    = {LECTURE NOTES IN COMPUTER SCIENCE},
  editor       = {Stenstrom, P and O'Boyle, M and Bodin, F and Cintra, M and McKee, SA},
  isbn         = {9783540715276},
  issn         = {0302-9743},
  keywords     = {IMPROVING DATA LOCALITY,WAVELET TRANSFORM,ARCHITECTURE,DESIGN},
  language     = {eng},
  location     = {Barcelona, Spain},
  pages        = {159--178},
  publisher    = {Springer},
  title        = {Finding and applying loop transformations for generating optimized FPGA implementations},
  url          = {http://dx.doi.org/10.1007/978-3-540-71528-3_11},
  volume       = {4050},
  year         = {2007},
}

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