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Does line edge roughness matter? FEOL and BEOL perspectives

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Organization
Abstract
Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimenional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that surface roughness does not degrade barrier performance of the AID Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.
Keywords
CHEMICALLY-AMPLIFIED RESISTS, ATOMIC LAYER DEPOSITION, SURFACE IMAGING PROCESS, POSITIVE-TONE, THIN-FILMS, LITHOGRAPHY, POLYMERS, MICROSTRUCTURE, SCATTERING, DIFFUSION

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MLA
LIN, QH, et al. “Does Line Edge Roughness Matter? FEOL and BEOL Perspectives.” ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, vol. 5039, 2003, pp. 1076–85.
APA
LIN, Q., Black, C., Detavernier, C., GIGNAC, L., GUARINI, K., HERBST, B., … SANCHEZ, M. (2003). Does line edge roughness matter? FEOL and BEOL perspectives. In ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2 (Vol. 5039, pp. 1076–1085).
Chicago author-date
LIN, QH, Christopher Black, Christophe Detavernier, L GIGNAC, K GUARINI, B HERBST, H KIM, P OLDIGES, K PETRILLO, and M SANCHEZ. 2003. “Does Line Edge Roughness Matter? FEOL and BEOL Perspectives.” In ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 5039:1076–85.
Chicago author-date (all authors)
LIN, QH, Christopher Black, Christophe Detavernier, L GIGNAC, K GUARINI, B HERBST, H KIM, P OLDIGES, K PETRILLO, and M SANCHEZ. 2003. “Does Line Edge Roughness Matter? FEOL and BEOL Perspectives.” In ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 5039:1076–1085.
Vancouver
1.
LIN Q, Black C, Detavernier C, GIGNAC L, GUARINI K, HERBST B, et al. Does line edge roughness matter? FEOL and BEOL perspectives. In: ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2. 2003. p. 1076–85.
IEEE
[1]
Q. LIN et al., “Does line edge roughness matter? FEOL and BEOL perspectives,” in ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2, 2003, vol. 5039, pp. 1076–1085.
@inproceedings{407038,
  abstract     = {Line edge roughness (LER) has been widely perceived to be one of the roadblocks to the continuing scaling of semiconductor devices. However, little evidence has been published on the impact of LER on device performance, particularly on the performance and the reliability of advanced interconnects. In this paper, we present such evidence from both the Front-End-Of-Line (FEOL) and Back-End-Of-Line (BEOL) standpoints. In the FEOL, we employed computer simulations to estimate the effects of LER on a number of performance parameters of sub-100nm transistors based on 2-dimensional and 3-dimenional device models. LER has been shown to affect both the average value and the variance of key device performance parameters for sub-100nm transistors. In the BEOL, we investigated the impact of LER on the performance of barrier layers in dual damascene copper interconnects. To this end, we emulated LER by roughening Si surfaces with controlled patterning by self-assembled diblock copolymers and reactive ion etching. In-situ time-resolved X-ray diffraction was used to study Cu diffusion through about 5nm Ta and TaN barrier layers deposited by plasma enhanced-atomic layer deposition (PE-ALD) on both smooth and rough surfaces. The X-ray diffraction results indicated that surface roughness does not degrade barrier performance of the AID Cu barriers. Mechanism of the roughness effects is also discussed. Line edge roughness is, however, expected to degrade copper interconnect performance by increasing copper electrical resistivity through enhanced electron surface scattering.},
  author       = {LIN, QH and Black, Christopher and Detavernier, Christophe and GIGNAC, L and GUARINI, K and HERBST, B and KIM, H and OLDIGES, P and PETRILLO, K and SANCHEZ, M},
  booktitle    = {ADVANCES IN RESIST TECHNOLOGY AND PROCESSING XX, PTS 1 AND 2},
  issn         = {0277-786X},
  keywords     = {CHEMICALLY-AMPLIFIED RESISTS,ATOMIC LAYER DEPOSITION,SURFACE IMAGING PROCESS,POSITIVE-TONE,THIN-FILMS,LITHOGRAPHY,POLYMERS,MICROSTRUCTURE,SCATTERING,DIFFUSION},
  language     = {eng},
  pages        = {1076--1085},
  title        = {Does line edge roughness matter? FEOL and BEOL perspectives},
  url          = {http://dx.doi.org/10.1117/12.487736},
  volume       = {5039},
  year         = {2003},
}

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