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NSL-BLRL: Efficient cache warm'up for sampled processor simulation

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MLA
Van Ertvelde, Luk, et al. “NSL-BLRL: Efficient Cache Warm’up for Sampled Processor Simulation.” 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS, IEEE COMPUTER SOC, 2006, pp. 168–75.
APA
Van Ertvelde, L., Hellebaut, F., Eeckhout, L., & De Bosschere, K. (2006). NSL-BLRL: Efficient cache warm’up for sampled processor simulation. In 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS (pp. 168–175). IEEE COMPUTER SOC.
Chicago author-date
Van Ertvelde, Luk, Filip Hellebaut, Lieven Eeckhout, and Koen De Bosschere. 2006. “NSL-BLRL: Efficient Cache Warm’up for Sampled Processor Simulation.” In 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS, 168–75. IEEE COMPUTER SOC.
Chicago author-date (all authors)
Van Ertvelde, Luk, Filip Hellebaut, Lieven Eeckhout, and Koen De Bosschere. 2006. “NSL-BLRL: Efficient Cache Warm’up for Sampled Processor Simulation.” In 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS, 168–175. IEEE COMPUTER SOC.
Vancouver
1.
Van Ertvelde L, Hellebaut F, Eeckhout L, De Bosschere K. NSL-BLRL: Efficient cache warm’up for sampled processor simulation. In: 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS. IEEE COMPUTER SOC; 2006. p. 168–75.
IEEE
[1]
L. Van Ertvelde, F. Hellebaut, L. Eeckhout, and K. De Bosschere, “NSL-BLRL: Efficient cache warm’up for sampled processor simulation,” in 39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS, 2006, pp. 168–175.
@inproceedings{406024,
  author       = {{Van Ertvelde, Luk and Hellebaut, Filip and Eeckhout, Lieven and De Bosschere, Koen}},
  booktitle    = {{39TH ANNUAL SIMULATION SYMPOSIUM, PROCEEDINGS}},
  isbn         = {{0-7695-2559-8}},
  issn         = {{1080-241X}},
  language     = {{eng}},
  pages        = {{168--175}},
  publisher    = {{IEEE COMPUTER SOC}},
  title        = {{NSL-BLRL: Efficient cache warm'up for sampled processor simulation}},
  year         = {{2006}},
}

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