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Novel electroless bumping technologies for MCM-D : bumping of single chips and straight-wall bumping on Cu metallisations

Herbert De Pauw (UGent) , Jan Vanfleteren (UGent) , Johan De Baets (UGent) and André Van Calster (UGent)
Author
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Abstract
To achieve a higher I/O count, increased speed along with increased performance, the flip-chip technique is one of the driving forces. Although flip-chip results in very reliable connections with high electrical performance, the high cost level must be reduced. Therefore it is essential to use a low cost bumping technique for both chip and interconnection substitute (Cu metallisation). The first part of this paper deals with a novel bumping technology for single chips, whereas the second part focuses on the development of a straight-wall bumping process on Cu bond pads. As conventional Al bonding pads on IC chips are not solderable, an under-bump-metallisation (UBM) is required for reflow, soldering. Electroless nickel/immersion gold (e-Ni/Au) has been widely accepted as UBM for this purpose. Conventionally, the e-Ni/Au bumping on ICs is carried our on wafer level. We developed a technology for the deposition of e-Ni/Au on single silicon chips or dice. Two challenges have to be dealt with first, the handling of the tiny chips/dice for the wet processing and second, the protection of the backside of the chips/dice in order to avoid unwanted nickel deposition. The navel method solves these two problems at one go and is extensively explained in this paper. Also to apply a solderable finish on Cu bond pads, e.g. chip or interconnection substrate with Cu metallisation, the maskless and reliable e-Ni/Au process can be called upon. Normally, the e-Ni/Au bumping on Cu pads differs from the e-Ni/Au bumping on Al pads only by the activation. We are currently investigating an innovative bumping technology in order to achieve Ni bumps with straight, walls on Cu bond pads. This e-Ni/Au process becomes more complex as we need to apply a removable mask and adjust the wet processing, but it should be possible to reach a very fine pitch. The core fundamentals of this bumping technology, as well as preliminary results, are presented in the second part of this paper.
Keywords
bumping, interconnection, electroless, flip-chip, technology

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Chicago
De Pauw, Herbert, Jan Vanfleteren, Johan De Baets, and André Van Calster. 2001. “Novel Electroless Bumping Technologies for MCM-D : Bumping of Single Chips and Straight-wall Bumping on Cu Metallisations.” In Proceedings of the Society of Photo-optical Instrumentation Engineers (spie), 4428:302–307. Bellingham, WA, USA: SPIE, the International Society for Optical Engineering.
APA
De Pauw, H., Vanfleteren, J., De Baets, J., & Van Calster, A. (2001). Novel electroless bumping technologies for MCM-D : bumping of single chips and straight-wall bumping on Cu metallisations. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE) (Vol. 4428, pp. 302–307). Presented at the International Conference on High-Density Interconnect and Systems Packaging (HD Int 2001), Bellingham, WA, USA: SPIE, the International Society for Optical Engineering.
Vancouver
1.
De Pauw H, Vanfleteren J, De Baets J, Van Calster A. Novel electroless bumping technologies for MCM-D : bumping of single chips and straight-wall bumping on Cu metallisations. PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE). Bellingham, WA, USA: SPIE, the International Society for Optical Engineering; 2001. p. 302–7.
MLA
De Pauw, Herbert, Jan Vanfleteren, Johan De Baets, et al. “Novel Electroless Bumping Technologies for MCM-D : Bumping of Single Chips and Straight-wall Bumping on Cu Metallisations.” Proceedings of the Society of Photo-optical Instrumentation Engineers (spie). Vol. 4428. Bellingham, WA, USA: SPIE, the International Society for Optical Engineering, 2001. 302–307. Print.
@inproceedings{401686,
  abstract     = {To achieve a higher I/O count, increased speed along with increased performance, the flip-chip technique is one of the driving forces. Although flip-chip results in very reliable connections with high electrical performance, the high cost level must be reduced. Therefore it is essential to use a low cost bumping technique for both chip and interconnection substitute (Cu metallisation). The first part of this paper deals with a novel bumping technology for single chips, whereas the second part focuses on the development of a straight-wall bumping process on Cu bond pads.
As conventional Al bonding pads on IC chips are not solderable, an under-bump-metallisation (UBM) is required for reflow, soldering. Electroless nickel/immersion gold (e-Ni/Au) has been widely accepted as UBM for this purpose. Conventionally, the e-Ni/Au bumping on ICs is carried our on wafer level. We developed a technology for the deposition of e-Ni/Au on single silicon chips or dice. Two challenges have to be dealt with first, the handling of the tiny chips/dice for the wet processing and second, the protection of the backside of the chips/dice in order to avoid unwanted nickel deposition. The navel method solves these two problems at one go and is extensively explained in this paper.
Also to apply a solderable finish on Cu bond pads, e.g. chip or interconnection substrate with Cu metallisation, the maskless and reliable e-Ni/Au process can be called upon. Normally, the e-Ni/Au bumping on Cu pads differs from the e-Ni/Au bumping on Al pads only by the activation. We are currently investigating an innovative bumping technology in order to achieve Ni bumps with straight, walls on Cu bond pads. This e-Ni/Au process becomes more complex as we need to apply a removable mask and adjust the wet processing, but it should be possible to reach a very fine pitch. The core fundamentals of this bumping technology, as well as preliminary results, are presented in the second part of this paper.},
  author       = {De Pauw, Herbert and Vanfleteren, Jan and De Baets, Johan and Van Calster, André},
  booktitle    = {PROCEEDINGS OF THE SOCIETY OF PHOTO-OPTICAL INSTRUMENTATION ENGINEERS (SPIE)},
  isbn         = {0-819441-39-2},
  issn         = {0277-786X},
  keywords     = {bumping,interconnection,electroless,flip-chip,technology},
  language     = {eng},
  location     = {Santa Clara, CA, USA},
  pages        = {302--307},
  publisher    = {SPIE, the International Society for Optical Engineering},
  title        = {Novel electroless bumping technologies for MCM-D : bumping of single chips and straight-wall bumping on Cu metallisations},
  volume       = {4428},
  year         = {2001},
}

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