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Abstract
This contribution presents the performance modeling of a super desktop with GPU and FPGA accelerators, using OpenCL for the GPU and a high-level synthesis compiler for the FPGAs. The performance model is used to evaluate the different high-level synthesis optimizations, taking into account the resource usage, and to compare the compute power of the FPGA with the GPU
Keywords
accelerators, programming toolchain, High Performance Computing, FPGA, GPU, computational intensity

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Citation

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Chicago
da Silva, Bruno, An Braeken, Erik D’Hollander, Abdellah Touhafi, Jan G Cornelis, and Jan Lemeire. 2013. “Study of Combining GPU/FPGA Accelerators for High-performance Computing.” In HLS4HPC Workshop at the 9th International Conference on High-Performance and Embedded Architectures and Compilers, ed. Philippe Coussy and Cyrille Chavet, 1–2. HiPEAC.
APA
da Silva, B., Braeken, A., D’Hollander, E., Touhafi, A., Cornelis, J. G., & Lemeire, J. (2013). Study of combining GPU/FPGA accelerators for high-performance computing. In P. Coussy & C. Chavet (Eds.), HLS4HPC workshop at the 9th International Conference on High-Performance and Embedded Architectures and Compilers (pp. 1–2). Presented at the High-Level Synthesis for High Performance Computing workshop, HiPEAC.
Vancouver
1.
da Silva B, Braeken A, D’Hollander E, Touhafi A, Cornelis JG, Lemeire J. Study of combining GPU/FPGA accelerators for high-performance computing. In: Coussy P, Chavet C, editors. HLS4HPC workshop at the 9th International Conference on High-Performance and Embedded Architectures and Compilers. HiPEAC; 2013. p. 1–2.
MLA
da Silva, Bruno, An Braeken, Erik D’Hollander, et al. “Study of Combining GPU/FPGA Accelerators for High-performance Computing.” HLS4HPC Workshop at the 9th International Conference on High-Performance and Embedded Architectures and Compilers. Ed. Philippe Coussy & Cyrille Chavet. HiPEAC, 2013. 1–2. Print.
@inproceedings{3227877,
  abstract     = {This contribution presents the performance modeling of a super desktop with GPU and FPGA accelerators, using OpenCL for the GPU and a high-level synthesis compiler for the FPGAs. The performance model is used to evaluate the different high-level synthesis optimizations, taking into account the resource usage, and to compare the compute power of the FPGA with the GPU},
  author       = {da Silva, Bruno and Braeken, An and D'Hollander, Erik and Touhafi, Abdellah and Cornelis, Jan G and Lemeire, Jan},
  booktitle    = {HLS4HPC workshop at the 9th International Conference on High-Performance and Embedded Architectures and Compilers},
  editor       = {Coussy, Philippe and Chavet, Cyrille},
  keyword      = {accelerators,programming toolchain,High Performance Computing,FPGA,GPU,computational intensity},
  language     = {eng},
  location     = {Berlin, Germany},
  pages        = {1--2},
  publisher    = {HiPEAC},
  title        = {Study of combining GPU/FPGA accelerators for high-performance computing},
  url          = {http://www-labsticc.univ-ubs.fr/{\texttildelow}chavet/orga/HLS4HPC\_2013/txt/EDH\_paper.pdf},
  year         = {2013},
}