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A jitter insensitive continuous-time ΣΔ modulator using transmission lines

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Abstract
This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1 % of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.
Keywords
CIRCUIT, SENSITIVITY

Citation

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MLA
Hernandez, L, Pieter Rombouts, E Prefasi, et al. “A Jitter Insensitive Continuous-time ΣΔ Modulator Using Transmission Lines.” ICECS 2004 : 11th IEEE International Conference on Electronics, Circuits and Systems. New York, NY, USA: IEEE, 2004. 109–112. Print.
APA
Hernandez, L, Rombouts, P., Prefasi, E., Paton, S., Garcia, M., & Lopez, C. (2004). A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS 2004 : 11th IEEE international conference on electronics, circuits and systems (pp. 109–112). Presented at the 11th IEEE International conference on Electronics, Circuits and Systems (ICICS 2004), New York, NY, USA: IEEE.
Chicago author-date
Hernandez, L, Pieter Rombouts, E Prefasi, S Paton, M Garcia, and C Lopez. 2004. “A Jitter Insensitive Continuous-time ΣΔ Modulator Using Transmission Lines.” In ICECS 2004 : 11th IEEE International Conference on Electronics, Circuits and Systems, 109–112. New York, NY, USA: IEEE.
Chicago author-date (all authors)
Hernandez, L, Pieter Rombouts, E Prefasi, S Paton, M Garcia, and C Lopez. 2004. “A Jitter Insensitive Continuous-time ΣΔ Modulator Using Transmission Lines.” In ICECS 2004 : 11th IEEE International Conference on Electronics, Circuits and Systems, 109–112. New York, NY, USA: IEEE.
Vancouver
1.
Hernandez L, Rombouts P, Prefasi E, Paton S, Garcia M, Lopez C. A jitter insensitive continuous-time ΣΔ modulator using transmission lines. ICECS 2004 : 11th IEEE international conference on electronics, circuits and systems. New York, NY, USA: IEEE; 2004. p. 109–12.
IEEE
[1]
L. Hernandez, P. Rombouts, E. Prefasi, S. Paton, M. Garcia, and C. Lopez, “A jitter insensitive continuous-time ΣΔ modulator using transmission lines,” in ICECS 2004 : 11th IEEE international conference on electronics, circuits and systems, Tel Aviv, Israel, 2004, pp. 109–112.
@inproceedings{319816,
  abstract     = {This work presents a prototype low pass continuous time sigma delta modulator which uses transmission lines in its loop filter rather than capacitive integrators. As has been shown in prior theoretical work, such a structure allows to desensitize the modulator against clock jitter and excess loop delay. The prototype single-bit modulator was designed for an oversampling ratio of 128. Clocked at 53.7 MHz it achieves a peak SNR of 67 dB. In an experiment with an excessive clock jitter of 1 % of the clock period, the SNDR is degraded by only 5dB compared to the case without jitter. This is 15dB better than an equivalent modulator with capacitive integrators.},
  author       = {Hernandez, L and Rombouts, Pieter and Prefasi, E and Paton, S and Garcia, M and Lopez, C},
  booktitle    = {ICECS 2004 : 11th IEEE international conference on electronics, circuits and systems},
  isbn         = {9780780387157},
  keywords     = {CIRCUIT,SENSITIVITY},
  language     = {eng},
  location     = {Tel Aviv, Israel},
  pages        = {109--112},
  publisher    = {IEEE},
  title        = {A jitter insensitive continuous-time ΣΔ modulator using transmission lines},
  url          = {http://dx.doi.org/10.1109/ICECS.2004.1399626},
  year         = {2004},
}

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