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Performance and toolchain of a combined GPU/FPGA desktop

Bruno da Silva UGent, An Braeken, Erik D'Hollander UGent, Abdellah Touhafi, Jan G. Cornelis and Jan Lemeire (2013) FPGA '13 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. p.274-274
abstract
Low-power, high-performance computing nowadays relies on accelerator cards to speed up the calculations. Combining the power of GPUs with the flexibility of FPGAs enlarges the scope of problems that can be accelerated. We describe the performance analysis of a desktop equipped with a GPU Tesla 2050 and an FPGA Virtex- 6 LX 240T. The balance between the I/O and the raw peak performance is analyzed using the roofline model. A well-tuned accelerator- based codesign, identifying the parallelism, the computation and data patterns of different classes of algorithms, will enable to maximize the performance of the combined GPU/FPGA system.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
FPGA, high-level synthesis, GPU, roofline model
in
FPGA '13 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
editor
Brad Hutchings and Vaughn Betz
pages
274 - 274
publisher
ACM
place of publication
New York, NY, USA
conference name
ACM/SIGDA international symposium on Field programmable gate arrays
conference location
Monterey, CA, USA
conference start
2013-01-11
conference end
2013-01-13
ISBN
9781450318877
language
English
UGent publication?
yes
classification
C3
copyright statement
I have retained and own the full copyright for this publication
id
3148367
handle
http://hdl.handle.net/1854/LU-3148367
date created
2013-02-27 11:28:22
date last changed
2017-12-19 12:50:25
@inproceedings{3148367,
  abstract     = {Low-power, high-performance computing nowadays relies on accelerator cards to speed up the calculations. Combining the power of GPUs with the flexibility of FPGAs enlarges the scope of problems that can be accelerated. We describe the performance analysis of a desktop equipped with a GPU Tesla 2050 and an FPGA Virtex- 6 LX 240T. The balance between the I/O and the raw peak performance is analyzed using the roofline model. A well-tuned accelerator- based codesign, identifying the parallelism, the computation and data patterns of different classes of algorithms, will enable to maximize the performance of the combined GPU/FPGA system.},
  author       = {da Silva, Bruno and Braeken, An and D'Hollander, Erik and Touhafi, Abdellah and Cornelis, Jan G.  and Lemeire, Jan},
  booktitle    = {FPGA '13 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays},
  editor       = {Hutchings, Brad and Betz, Vaughn},
  isbn         = {9781450318877},
  keyword      = {FPGA,high-level synthesis,GPU,roofline model},
  language     = {eng},
  location     = {Monterey, CA, USA},
  pages        = {274--274},
  publisher    = {ACM},
  title        = {Performance and toolchain of a combined GPU/FPGA desktop},
  year         = {2013},
}

Chicago
da Silva, Bruno, An Braeken, Erik D’Hollander, Abdellah Touhafi, Jan G. Cornelis, and Jan Lemeire. 2013. “Performance and Toolchain of a Combined GPU/FPGA Desktop.” In FPGA  ’13 Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, ed. Brad Hutchings and Vaughn Betz, 274–274. New York, NY, USA: ACM.
APA
da Silva, B., Braeken, A., D’Hollander, E., Touhafi, A., Cornelis, J. G., & Lemeire, J. (2013). Performance and toolchain of a combined GPU/FPGA desktop. In B. Hutchings & V. Betz (Eds.), FPGA  ’13 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays (pp. 274–274). Presented at the ACM/SIGDA international symposium on Field programmable gate arrays, New York, NY, USA: ACM.
Vancouver
1.
da Silva B, Braeken A, D’Hollander E, Touhafi A, Cornelis JG, Lemeire J. Performance and toolchain of a combined GPU/FPGA desktop. In: Hutchings B, Betz V, editors. FPGA  ’13 Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays. New York, NY, USA: ACM; 2013. p. 274–274.
MLA
da Silva, Bruno, An Braeken, Erik D’Hollander, et al. “Performance and Toolchain of a Combined GPU/FPGA Desktop.” FPGA  ’13 Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays. Ed. Brad Hutchings & Vaughn Betz. New York, NY, USA: ACM, 2013. 274–274. Print.