Advanced search
1 file | 292.20 KB Add to list

A dynamically reconfigurable pattern matcher for regular expressions on FPGA

Author
Organization
Abstract
In this article we describe how to expand a partially dynamic reconfig- urable pattern matcher for regular expressions presented in previous work by Di- vyasree and Rajashekar [2]. The resulting, extended, pattern matcher is fully dynamically reconfigurable. First, the design is adapted for use with parameterisable configurations, a method for Dynamic Circuit Specialization. Using parameteris- able configurations allows us to achieve the same area gains as the hand crafted reconfigurable design, with the benefit that parameterisable configurations can be applied automatically. This results in a design that is more easily adaptable to spe- cific applications and allows for an easier design exploration. Additionally, the pa- rameterisable configuration implementation is also generated automatically, which greatly reduces the design overhead of using dynamic reconfiguration. Secondly, we propose a number of expansions to the original design to overcome several limitations in the original design that constrain the dynamic reconfigurability of the pattern matcher. We propose two different solutions to dynamically change the character that is matched in a certain block. The resulting pattern matcher, after these changes, is fully dynamically reconfigurable, all aspects of the implemented regular expression can be changed at run-time.
Keywords
Run-time reconfiguration, FPGA, Dynamic Circuit Specialization

Downloads

  • IOS-Book-Article.pdf
    • full text
    • |
    • open access
    • |
    • PDF
    • |
    • 292.20 KB

Citation

Please use this url to cite or link to this publication:

MLA
Davidson, Tom et al. “A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA.” Advances in Parallel Computing. Ed. Koen De Bosschere et al. Vol. 22. Amsterdam, The Netherlands: IOS Press, 2012. 611–618. Print.
APA
Davidson, Tom, Merlier, M., Bruneel, K., & Stroobandt, D. (2012). A dynamically reconfigurable pattern matcher for regular expressions on FPGA. In K. De Bosschere, E. D’Hollander, G. R. Joubert, D. Padua, & F. Peters (Eds.), Advances in Parallel Computing (Vol. 22, pp. 611–618). Presented at the Parallel Computing with FPGAs 2011 (ParaFPGA 2011), Amsterdam, The Netherlands: IOS Press.
Chicago author-date
Davidson, Tom, Mattias Merlier, Karel Bruneel, and Dirk Stroobandt. 2012. “A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA.” In Advances in Parallel Computing, ed. Koen De Bosschere, EH D’Hollander, Gerhard R Joubert, D Padua, and F Peters, 22:611–618. Amsterdam, The Netherlands: IOS Press.
Chicago author-date (all authors)
Davidson, Tom, Mattias Merlier, Karel Bruneel, and Dirk Stroobandt. 2012. “A Dynamically Reconfigurable Pattern Matcher for Regular Expressions on FPGA.” In Advances in Parallel Computing, ed. Koen De Bosschere, EH D’Hollander, Gerhard R Joubert, D Padua, and F Peters, 22:611–618. Amsterdam, The Netherlands: IOS Press.
Vancouver
1.
Davidson T, Merlier M, Bruneel K, Stroobandt D. A dynamically reconfigurable pattern matcher for regular expressions on FPGA. In: De Bosschere K, D’Hollander E, Joubert GR, Padua D, Peters F, editors. Advances in Parallel Computing. Amsterdam, The Netherlands: IOS Press; 2012. p. 611–8.
IEEE
[1]
T. Davidson, M. Merlier, K. Bruneel, and D. Stroobandt, “A dynamically reconfigurable pattern matcher for regular expressions on FPGA,” in Advances in Parallel Computing, Ghent, Belgium, 2012, vol. 22, pp. 611–618.
@inproceedings{3110395,
  abstract     = {In this article we describe how to expand a partially dynamic reconfig- urable pattern matcher for regular expressions presented in previous work by Di- vyasree and Rajashekar [2]. The resulting, extended, pattern matcher is fully dynamically reconfigurable. First, the design is adapted for use with parameterisable configurations, a method for Dynamic Circuit Specialization. Using parameteris- able configurations allows us to achieve the same area gains as the hand crafted reconfigurable design, with the benefit that parameterisable configurations can be applied automatically. This results in a design that is more easily adaptable to spe- cific applications and allows for an easier design exploration. Additionally, the pa- rameterisable configuration implementation is also generated automatically, which greatly reduces the design overhead of using dynamic reconfiguration. Secondly, we propose a number of expansions to the original design to overcome several limitations in the original design that constrain the dynamic reconfigurability of the pattern matcher. We propose two different solutions to dynamically change the character that is matched in a certain block. The resulting pattern matcher, after these changes, is fully dynamically reconfigurable, all aspects of the implemented regular expression can be changed at run-time.},
  author       = {Davidson, Tom and Merlier, Mattias and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {Advances in Parallel Computing},
  editor       = {De Bosschere, Koen and D'Hollander, EH and Joubert, Gerhard R and Padua, D and Peters, F},
  isbn         = {9781614990406},
  issn         = {1879-808X},
  keywords     = {Run-time reconfiguration,FPGA,Dynamic Circuit Specialization},
  language     = {eng},
  location     = {Ghent, Belgium},
  pages        = {611--618},
  publisher    = {IOS Press},
  title        = {A dynamically reconfigurable pattern matcher for regular expressions on FPGA},
  url          = {http://dx.doi.org/10.3233/978-1-61499-041-3-611},
  volume       = {22},
  year         = {2012},
}

Altmetric
View in Altmetric