Stochastic modeling-based variability analysis of on-chip interconnects
- Author
- Dries Vande Ginste (UGent) , Daniël De Zutter (UGent) , Dirk Deschrijver (UGent) , Tom Dhaene (UGent) , Paolo Manfredi and Flavio Canavero
- Organization
- Abstract
- In this paper, a novel stochastic modeling strategy is constructed that allows assessment of the parameter variability effects induced by the manufacturing process of on-chip interconnects. The strategy adopts a three-step approach. First, a very accurate electromagnetic modeling technique yields the per unit length (p.u.l.) transmission line parameters of the on-chip interconnect structures. Second, parameterized macromodels of these p.u.l. parameters are constructed. Third, a stochastic Galerkin method is implemented to solve the pertinent stochastic telegrapher's equations. The new methodology is illustrated with meaningful design examples, demonstrating its accuracy and efficiency. Improvements and advantages with respect to the state-of-the-art are clearly highlighted.
- Keywords
- LINES, Multiconductor transmission lines (MTLs), PARAMETERS, VECTOR, FREQUENCY-DOMAIN, POLYNOMIAL CHAOS, on-chip interconnects, stochastic Galerkin method (SGM), variability analysis
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-2984280
- MLA
- Vande Ginste, Dries, et al. “Stochastic Modeling-Based Variability Analysis of on-Chip Interconnects.” IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, vol. 2, no. 7, 2012, pp. 1182–92, doi:10.1109/TCPMT.2012.2192274.
- APA
- Vande Ginste, D., De Zutter, D., Deschrijver, D., Dhaene, T., Manfredi, P., & Canavero, F. (2012). Stochastic modeling-based variability analysis of on-chip interconnects. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2(7), 1182–1192. https://doi.org/10.1109/TCPMT.2012.2192274
- Chicago author-date
- Vande Ginste, Dries, Daniël De Zutter, Dirk Deschrijver, Tom Dhaene, Paolo Manfredi, and Flavio Canavero. 2012. “Stochastic Modeling-Based Variability Analysis of on-Chip Interconnects.” IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2 (7): 1182–92. https://doi.org/10.1109/TCPMT.2012.2192274.
- Chicago author-date (all authors)
- Vande Ginste, Dries, Daniël De Zutter, Dirk Deschrijver, Tom Dhaene, Paolo Manfredi, and Flavio Canavero. 2012. “Stochastic Modeling-Based Variability Analysis of on-Chip Interconnects.” IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 2 (7): 1182–1192. doi:10.1109/TCPMT.2012.2192274.
- Vancouver
- 1.Vande Ginste D, De Zutter D, Deschrijver D, Dhaene T, Manfredi P, Canavero F. Stochastic modeling-based variability analysis of on-chip interconnects. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY. 2012;2(7):1182–92.
- IEEE
- [1]D. Vande Ginste, D. De Zutter, D. Deschrijver, T. Dhaene, P. Manfredi, and F. Canavero, “Stochastic modeling-based variability analysis of on-chip interconnects,” IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, vol. 2, no. 7, pp. 1182–1192, 2012.
@article{2984280,
abstract = {{In this paper, a novel stochastic modeling strategy is constructed that allows assessment of the parameter variability effects induced by the manufacturing process of on-chip interconnects. The strategy adopts a three-step approach. First, a very accurate electromagnetic modeling technique yields the per unit length (p.u.l.) transmission line parameters of the on-chip interconnect structures. Second, parameterized macromodels of these p.u.l. parameters are constructed. Third, a stochastic Galerkin method is implemented to solve the pertinent stochastic telegrapher's equations. The new methodology is illustrated with meaningful design examples, demonstrating its accuracy and efficiency. Improvements and advantages with respect to the state-of-the-art are clearly highlighted.}},
author = {{Vande Ginste, Dries and De Zutter, Daniël and Deschrijver, Dirk and Dhaene, Tom and Manfredi, Paolo and Canavero, Flavio}},
issn = {{2156-3950}},
journal = {{IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY}},
keywords = {{LINES,Multiconductor transmission lines (MTLs),PARAMETERS,VECTOR,FREQUENCY-DOMAIN,POLYNOMIAL CHAOS,on-chip interconnects,stochastic Galerkin method (SGM),variability analysis}},
language = {{eng}},
number = {{7}},
pages = {{1182--1192}},
title = {{Stochastic modeling-based variability analysis of on-chip interconnects}},
url = {{http://dx.doi.org/10.1109/TCPMT.2012.2192274}},
volume = {{2}},
year = {{2012}},
}
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