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A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time

Xin Yin (UGent) , Jasmien Put (UGent) , Jochen Verbrugghe (UGent) , Jan Gillis (UGent) , Xing-Zhi Qiu (UGent) , Johan Bauwelinck (UGent) , Jan Vandewege (UGent) , HG Krimmel and M Achouche
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Abstract
Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conventional AC-coupled BM- RX has an inherent tradeoff between short settling time and decision threshold droop, which makes an RX settling time shorter than 400ns hard to achieve. Some techniques have been developed to overcome this limitation, demonstrating a settling time of 150 to 200ns. Our previous work uses feed-forward automatic offset compensation (AOC) to achieve a response time as short as 25.6ns. However, a feed-forward scheme using peak detectors is intrinsically less accurate and results in relatively high power consumption. In this paper, we present a DC-coupled 10Gb/s BM-TIA and burst-mode limiting amplifier (BM- LA) chipset that uses a feedback type AOC circuit with switchable loop BW. This new technique is capable of removing input DC offset in less than 75ns, and offers continuous decision threshold tracking during payload, to cope with the maximum length of CID. The differential TIA output port senses a CM reset signal provided by the succeeding BM-LA, and activates an on-chip reset and lock function. This BM-LA also integrates auto reset/activity generation circuits providing the AOC BW switching signal, so that this time-critical signal is not required from the PON system.

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Chicago
Yin, Xin, Jasmien Put, Jochen Verbrugghe, Jan Gillis, Xing-Zhi Qiu, Johan Bauwelinck, Jan Vandewege, HG Krimmel, and M Achouche. 2012. “A 10Gb/s Burst-mode TIA with On-chip Reset/lock CM Signaling Detection and Limiting Amplifier with a 75ns Settling Time.” In 2012 IEEE International Solid-State Circuits Conference (ISSCC), 416–418. Piscataway, NJ, USA: IEEE.
APA
Yin, X., Put, J., Verbrugghe, J., Gillis, J., Qiu, X.-Z., Bauwelinck, J., Vandewege, J., et al. (2012). A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time. 2012 IEEE International Solid-State Circuits Conference (ISSCC) (pp. 416–418). Presented at the 2012 IEEE International Solid-State Circuits Conference (ISSCC - 2012), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Yin X, Put J, Verbrugghe J, Gillis J, Qiu X-Z, Bauwelinck J, et al. A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time. 2012 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway, NJ, USA: IEEE; 2012. p. 416–8.
MLA
Yin, Xin et al. “A 10Gb/s Burst-mode TIA with On-chip Reset/lock CM Signaling Detection and Limiting Amplifier with a 75ns Settling Time.” 2012 IEEE International Solid-State Circuits Conference (ISSCC). Piscataway, NJ, USA: IEEE, 2012. 416–418. Print.
@inproceedings{2983890,
  abstract     = {Emerging symmetric 10Gb/s passive optical network (PON) systems aim at high network transmission efficiency by reducing the RX settling time that is needed for RX amplitude recovery in burst-mode (BM). A conventional AC-coupled BM- RX has an inherent tradeoff between short settling time and decision threshold droop, which makes an RX settling time shorter than 400ns hard to achieve. Some techniques have been developed to overcome this limitation, demonstrating a settling time of 150 to 200ns. Our previous work uses feed-forward automatic offset compensation (AOC) to achieve a response time as short as 25.6ns. However, a feed-forward scheme using peak detectors is intrinsically less accurate and results in relatively high power consumption. In this paper, we present a DC-coupled 10Gb/s BM-TIA and burst-mode limiting amplifier (BM- LA) chipset that uses a feedback type AOC circuit with switchable loop BW. This new technique is capable of removing input DC offset in less than 75ns, and offers continuous decision threshold tracking during payload, to cope with the maximum length of CID. The differential TIA output port senses a CM reset signal provided by the succeeding BM-LA, and activates an on-chip reset and lock function. This BM-LA also integrates auto reset/activity generation circuits providing the AOC BW switching signal, so that this time-critical signal is not required from the PON system.},
  author       = {Yin, Xin and Put, Jasmien and Verbrugghe, Jochen and Gillis, Jan and Qiu, Xing-Zhi and Bauwelinck, Johan and Vandewege, Jan and Krimmel, HG and Achouche, M},
  booktitle    = {2012 IEEE International Solid-State Circuits Conference (ISSCC)},
  isbn         = {9781467303767},
  language     = {eng},
  location     = {San Francisco, CA, USA},
  pages        = {416--418},
  publisher    = {IEEE},
  title        = {A 10Gb/s burst-mode TIA with on-chip reset/lock CM signaling detection and limiting amplifier with a 75ns settling time},
  url          = {http://dx.doi.org/10.1109/ISSCC.2012.6177071},
  year         = {2012},
}

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