3D-stacking of UTCPs as a module miniaturization technology
- Author
- Swarnakamal Priyabadini (UGent) , An Gielen (UGent) , Kristof Dhaenens (UGent) , Wim Christiaens (UGent) , Steven Van Put (UGent) , Gerhard Kunkel, Anders Erik Petersen and Jan Vanfleteren (UGent)
- Organization
- Abstract
- 3D-stacking of Ultra Thin Chip Packages (UTCP’s) – one of the emerging technologies in the field of high density integration - is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. This paper describes an approach to produce miniaturized modular packages by using Ultrathin Chip Package Technology, stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (~20 µm) within two 20 µm thick spin-on polyimide layers resulting in a thin flexible chip package of thickness ~50 µm. Stacking of the 4 layers of UTCPs by using 25 µm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ~300 µm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. After processing and testing, the stacks can be easily mounted within functional demonstrators (e.g, Hearing Aid device, etc) replacing single silicon die of almost same size, but with 4 times output.
- Keywords
- TH-interconnection, Vacuum Lamination, 3D stacking, UTCP
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-2970707
- MLA
- Priyabadini, Swarnakamal, et al. “3D-Stacking of UTCPs as a Module Miniaturization Technology.” 44th International Symposium on Microelectronics, Proceedings, International Microelectronics and Packaging Society (IMAPS), 2011, pp. 463–68.
- APA
- Priyabadini, S., Gielen, A., Dhaenens, K., Christiaens, W., Van Put, S., Kunkel, G., … Vanfleteren, J. (2011). 3D-stacking of UTCPs as a module miniaturization technology. 44th International Symposium on Microelectronics, Proceedings, 463–468. USA: International Microelectronics and Packaging Society (IMAPS).
- Chicago author-date
- Priyabadini, Swarnakamal, An Gielen, Kristof Dhaenens, Wim Christiaens, Steven Van Put, Gerhard Kunkel, Anders Erik Petersen, and Jan Vanfleteren. 2011. “3D-Stacking of UTCPs as a Module Miniaturization Technology.” In 44th International Symposium on Microelectronics, Proceedings, 463–68. USA: International Microelectronics and Packaging Society (IMAPS).
- Chicago author-date (all authors)
- Priyabadini, Swarnakamal, An Gielen, Kristof Dhaenens, Wim Christiaens, Steven Van Put, Gerhard Kunkel, Anders Erik Petersen, and Jan Vanfleteren. 2011. “3D-Stacking of UTCPs as a Module Miniaturization Technology.” In 44th International Symposium on Microelectronics, Proceedings, 463–468. USA: International Microelectronics and Packaging Society (IMAPS).
- Vancouver
- 1.Priyabadini S, Gielen A, Dhaenens K, Christiaens W, Van Put S, Kunkel G, et al. 3D-stacking of UTCPs as a module miniaturization technology. In: 44th International Symposium on Microelectronics, Proceedings. USA: International Microelectronics and Packaging Society (IMAPS); 2011. p. 463–8.
- IEEE
- [1]S. Priyabadini et al., “3D-stacking of UTCPs as a module miniaturization technology,” in 44th International Symposium on Microelectronics, Proceedings, Long Beach, CA, USA, 2011, pp. 463–468.
@inproceedings{2970707,
abstract = {{3D-stacking of Ultra Thin Chip Packages (UTCP’s) – one of the emerging technologies in the field of high density integration - is presented here. This technology is developed to increase the functionality of the electronic devices and to raise the comfort zone by reducing the overall size and weight of the package. This has a bright future in the area of mobile communication, medical equipments like hearing aids, implants, patient monitoring. This paper describes an approach to produce miniaturized modular packages by using Ultrathin Chip Package Technology, stacking and through-hole (TH) interconnection technology. UTCP technology is a board level packaging concept, based on embedding of ultra-thin chips (~20 µm) within two 20 µm thick spin-on polyimide layers resulting in a thin flexible chip package of thickness ~50 µm. Stacking of the 4 layers of UTCPs by using 25 µm thick layers of adhesive films and vacuum lamination processes results in stacked UTCP modules of total thickness ~300 µm. The connection to the different layers of the UTCPs is realized by drilling THs on the outer contact pads on the stacked packages, followed by metallization of these THs by Cu electroless deposition, electroplating and finally metal structuring. After processing and testing, the stacks can be easily mounted within functional demonstrators (e.g, Hearing Aid device, etc) replacing single silicon die of almost same size, but with 4 times output.}},
author = {{Priyabadini, Swarnakamal and Gielen, An and Dhaenens, Kristof and Christiaens, Wim and Van Put, Steven and Kunkel, Gerhard and Petersen, Anders Erik and Vanfleteren, Jan}},
booktitle = {{44th International Symposium on Microelectronics, Proceedings}},
keywords = {{TH-interconnection,Vacuum Lamination,3D stacking,UTCP}},
language = {{eng}},
location = {{Long Beach, CA, USA}},
pages = {{463--468}},
publisher = {{International Microelectronics and Packaging Society (IMAPS)}},
title = {{3D-stacking of UTCPs as a module miniaturization technology}},
url = {{http://www.imaps.org/abstracts/system/new/abstract_preview.asp?abstract=11imaps158}},
year = {{2011}},
}