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A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth

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Abstract
In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW.
Keywords
A/D conversion, Continuous time sigma delta modulation, Pulsewidth modulation, Self-oscillation

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Citation

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MLA
Woestyn, Pierre, et al. “A Selectable-Bandwidth 3.5 MW, 0.03 Mm(2) Self-Oscillating Sigma Delta Modulator with 71 DB Dynamic Range at 5 MHz and 65 DB at 10 MHz Bandwidth.” ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 72, no. 1, 2012, pp. 55–63, doi:10.1007/s10470-012-9835-6.
APA
Woestyn, P., Rombouts, P., Xing, X., & Gielen, G. (2012). A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, 72(1), 55–63. https://doi.org/10.1007/s10470-012-9835-6
Chicago author-date
Woestyn, Pierre, Pieter Rombouts, Xinpeng Xing, and Georges Gielen. 2012. “A Selectable-Bandwidth 3.5 MW, 0.03 Mm(2) Self-Oscillating Sigma Delta Modulator with 71 DB Dynamic Range at 5 MHz and 65 DB at 10 MHz Bandwidth.” ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 72 (1): 55–63. https://doi.org/10.1007/s10470-012-9835-6.
Chicago author-date (all authors)
Woestyn, Pierre, Pieter Rombouts, Xinpeng Xing, and Georges Gielen. 2012. “A Selectable-Bandwidth 3.5 MW, 0.03 Mm(2) Self-Oscillating Sigma Delta Modulator with 71 DB Dynamic Range at 5 MHz and 65 DB at 10 MHz Bandwidth.” ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 72 (1): 55–63. doi:10.1007/s10470-012-9835-6.
Vancouver
1.
Woestyn P, Rombouts P, Xing X, Gielen G. A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth. ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING. 2012;72(1):55–63.
IEEE
[1]
P. Woestyn, P. Rombouts, X. Xing, and G. Gielen, “A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth,” ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, vol. 72, no. 1, pp. 55–63, 2012.
@article{2959071,
  abstract     = {{In this paper we present a dual-mode third order continuous time Sigma Delta modulator that combines noise shaping and pulse-width-modulation (PWM). In our 0.18 micro-m CMOS prototype chip the clock frequency equals 1 GHz, but the PWM carrier is only around 125 MHz. By adjusting the loop filter, the ADC bandwidth can be set to 5 or 10 MHz. In the 5 MHz mode the peak SNDR equals 64 dB and the dynamic range 71 dB. In the 10 MHz mode the peak SNDR equals 58 dB and the DR 65 dB. This performance is achieved at an attractively low silicon area of 0.03 mm^2 and a power consumption of 3.5 mW.}},
  author       = {{Woestyn, Pierre and Rombouts, Pieter and Xing, Xinpeng and Gielen, Georges}},
  issn         = {{0925-1030}},
  journal      = {{ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING}},
  keywords     = {{A/D conversion,Continuous time sigma delta modulation,Pulsewidth modulation,Self-oscillation}},
  language     = {{eng}},
  number       = {{1}},
  pages        = {{55--63}},
  title        = {{A selectable-bandwidth 3.5 mW, 0.03 mm(2) self-oscillating Sigma Delta modulator with 71 dB dynamic range at 5 MHz and 65 dB at 10 MHz bandwidth}},
  url          = {{http://doi.org/10.1007/s10470-012-9835-6}},
  volume       = {{72}},
  year         = {{2012}},
}

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