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Synchronous delay based UWB pulse generator in FPGA

(2012) IEICE ELECTRONICS EXPRESS. 9(9). p.868-873
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Abstract
This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150 MHz, we generate RF pulse of 300 MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.
Keywords
synchronous delay, FPGA, pulse generator, transmitters, UWB

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Citation

Please use this url to cite or link to this publication:

MLA
Duraiswamy, Punithavathi, Xiao Li, Johan Bauwelinck, et al. “Synchronous Delay Based UWB Pulse Generator in FPGA.” IEICE ELECTRONICS EXPRESS 9.9 (2012): 868–873. Print.
APA
Duraiswamy, P., Li, X., Bauwelinck, J., Vandewege, J., Vaes, P., & Teughels, S. (2012). Synchronous delay based UWB pulse generator in FPGA. IEICE ELECTRONICS EXPRESS, 9(9), 868–873.
Chicago author-date
Duraiswamy, Punithavathi, Xiao Li, Johan Bauwelinck, Jan Vandewege, Peter Vaes, and Stephanie Teughels. 2012. “Synchronous Delay Based UWB Pulse Generator in FPGA.” Ieice Electronics Express 9 (9): 868–873.
Chicago author-date (all authors)
Duraiswamy, Punithavathi, Xiao Li, Johan Bauwelinck, Jan Vandewege, Peter Vaes, and Stephanie Teughels. 2012. “Synchronous Delay Based UWB Pulse Generator in FPGA.” Ieice Electronics Express 9 (9): 868–873.
Vancouver
1.
Duraiswamy P, Li X, Bauwelinck J, Vandewege J, Vaes P, Teughels S. Synchronous delay based UWB pulse generator in FPGA. IEICE ELECTRONICS EXPRESS. 2012;9(9):868–73.
IEEE
[1]
P. Duraiswamy, X. Li, J. Bauwelinck, J. Vandewege, P. Vaes, and S. Teughels, “Synchronous delay based UWB pulse generator in FPGA,” IEICE ELECTRONICS EXPRESS, vol. 9, no. 9, pp. 868–873, 2012.
@article{2941139,
  abstract     = {This paper presents an architecture for generating UWB pulses with a high centre frequency accuracy. The architecture allows to generate frequencies twice that of the FPGA clock using synchronous delays and is implementable in all types of FPGA. With a FPGA clock of 150 MHz, we generate RF pulse of 300 MHz with a maximum fractional bandwidth of 30%. The architecture also allows pulse width increment in steps of the clock period.},
  author       = {Duraiswamy, Punithavathi and Li, Xiao and Bauwelinck, Johan and Vandewege, Jan and Vaes, Peter and Teughels, Stephanie},
  issn         = {1349-2543},
  journal      = {IEICE ELECTRONICS EXPRESS},
  keywords     = {synchronous delay,FPGA,pulse generator,transmitters,UWB},
  language     = {eng},
  number       = {9},
  pages        = {868--873},
  title        = {Synchronous delay based UWB pulse generator in FPGA},
  url          = {http://dx.doi.org/10.1587/elex.9.868},
  volume       = {9},
  year         = {2012},
}

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