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Mapping logic to reconfigurable FPGA routing

Karel Heyse (UGent) , Karel Bruneel (UGent) and Dirk Stroobandt (UGent)
Author
Organization
Project
EU - FP7 FASTER project (#287804)
Abstract
Parameterised configurations for FPGAs are configuration bitstreams of which part of the bits are defined as Boolean functions of parameters. By evaluating these Boolean functions using different parameter values, it is possible to quickly and efficiently derive specialised configuration bitstreams with different properties. An important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation. Generating and using parameterised configurations requires a new FPGA tool flow. In this paper we present an algorithm for technology mapping of parameterised designs that can exploit the reconfigurability of the logic blocks and routing of the FPGA. This algorithm, called TCONMAP, is based on “Cut enumeration, cut ranking, node selection”. As part of it, a new method to calculate the feasibility of cuts based on the Binary Decision Diagrams (BDD) of their local function is proposed.
Keywords
Technology mapping, Run-time reconfiguration, FPGA

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Citation

Please use this url to cite or link to this publication:

Chicago
Heyse, Karel, Karel Bruneel, and Dirk Stroobandt. 2012. “Mapping Logic to Reconfigurable FPGA Routing.” In 22nd International Conference on Field Programmable Logic and Applications, Proceedings, 315–321. Piscataway, NJ, USA: IEEE.
APA
Heyse, K., Bruneel, K., & Stroobandt, D. (2012). Mapping logic to reconfigurable FPGA routing. 22nd International Conference on Field Programmable Logic and Applications, Proceedings (pp. 315–321). Presented at the 22nd International Conference on Field Programmable Logic and Applications (FPL - 2012), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Heyse K, Bruneel K, Stroobandt D. Mapping logic to reconfigurable FPGA routing. 22nd International Conference on Field Programmable Logic and Applications, Proceedings. Piscataway, NJ, USA: IEEE; 2012. p. 315–21.
MLA
Heyse, Karel, Karel Bruneel, and Dirk Stroobandt. “Mapping Logic to Reconfigurable FPGA Routing.” 22nd International Conference on Field Programmable Logic and Applications, Proceedings. Piscataway, NJ, USA: IEEE, 2012. 315–321. Print.
@inproceedings{2914001,
  abstract     = {Parameterised configurations for FPGAs are configuration bitstreams of which part of the bits are defined as Boolean functions of parameters. By evaluating these Boolean functions using different parameter values, it is possible to quickly and efficiently derive specialised configuration bitstreams with different properties. An important application of parameterised configurations is the generation of specialised configuration bitstreams for Dynamic Circuit Specialisation. Generating and using parameterised configurations requires a new FPGA tool flow. In this paper we present an algorithm for technology mapping of parameterised designs that can exploit the reconfigurability of the logic blocks and routing of the FPGA. This algorithm, called TCONMAP, is based on {\textquotedblleft}Cut enumeration, cut ranking, node selection{\textquotedblright}. As part of it, a new method to calculate the feasibility of cuts based on the Binary Decision Diagrams (BDD) of their local function is proposed.},
  author       = {Heyse, Karel and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {22nd International Conference on Field Programmable Logic and Applications, Proceedings},
  isbn         = {9781467322553},
  language     = {eng},
  location     = {Oslo, Norway},
  pages        = {315--321},
  publisher    = {IEEE},
  title        = {Mapping logic to reconfigurable FPGA routing},
  url          = {http://dx.doi.org/10.1109/FPL.2012.6339224},
  year         = {2012},
}

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