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Creating quasistatic, parameterized FPGA designs

Jo Pletinckx, R VLAMINCK and Jan Vandewege UGent (2003) EDN. 48(17).
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
journal title
EDN
EDN
volume
48
issue
17
pages
69-+ pages
publisher
CAHNERS-DENVER PUBLISHING CO
Web of Science type
Article
Web of Science id
000184564400009
JCR category
ENGINEERING, ELECTRICAL & ELECTRONIC
JCR impact factor
0.104 (2003)
JCR rank
186/205 (2003)
JCR quartile
4 (2003)
ISSN
0012-7515
language
English
UGent publication?
yes
classification
A1
id
216505
handle
http://hdl.handle.net/1854/LU-216505
date created
2004-05-13 10:37:00
date last changed
2016-12-19 15:38:01
@article{216505,
  author       = {Pletinckx, Jo and VLAMINCK, R and Vandewege, Jan},
  issn         = {0012-7515},
  journal      = {EDN},
  language     = {eng},
  number       = {17},
  pages        = {69-+},
  publisher    = {CAHNERS-DENVER PUBLISHING CO},
  title        = {Creating quasistatic, parameterized FPGA designs},
  volume       = {48},
  year         = {2003},
}

Chicago
Pletinckx, Jo, R VLAMINCK, and Jan Vandewege. 2003. “Creating Quasistatic, Parameterized FPGA Designs.” EDN 48 (17): 69.
APA
Pletinckx, J., VLAMINCK, R., & Vandewege, J. (2003). Creating quasistatic, parameterized FPGA designs. EDN, 48(17), 69.
Vancouver
1.
Pletinckx J, VLAMINCK R, Vandewege J. Creating quasistatic, parameterized FPGA designs. EDN. CAHNERS-DENVER PUBLISHING CO; 2003;48(17):69.
MLA
Pletinckx, Jo, R VLAMINCK, and Jan Vandewege. “Creating Quasistatic, Parameterized FPGA Designs.” EDN 48.17 (2003): 69. Print.