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A mechanistic performance model for superscalar in-order processors

Maximilien Breughe UGent, Stijn Eyerman UGent and Lieven Eeckhout UGent (2012) IEEE international symposium on performance analysis of systems and software, Proceedings. p.14-24
abstract
Mechanistic processor performance modeling builds an analytical model from understanding the underlying mechanisms in the processor and provides fundamental insight in program-microarchitecture interactions, as well as microarchitecture structure scaling trends and interactions. Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors. We find mechanistic modeling for in-order processors to be more challenging compared to out-of-order processors because the latter are designed to hide latencies, and hence from a modeling perspective, detailed modeling of instruction execution latencies and dependencies is not required. The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch mispredictions, and achieves an average performance prediction error of 2.5% compared to detailed cycle-accurate simulation. We extensively evaluate the model’s accuracy and we demonstrate its usefulness through three applications: (i) we compare in-order versus out-of-order performance, (ii) we quantify the impact of compiler optimizations on in-order performance, and (iii) we perform a power/performance design space exploration.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
micro architecture, resource scaling, embedded system, compiler optimization, cpi stack, microprocessor, mechanistic model, computer architecture, design space exploration, superscalar in-order processor, performance
in
IEEE international symposium on performance analysis of systems and software, Proceedings
article_number
2
pages
14 - 24
publisher
IEEE
place of publication
Piscataway, NJ, USA
conference name
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS - 2012)
conference location
New Brunswick, NJ, USA
conference start
2012-04-01
conference end
2012-04-03
ISBN
9781467311441
language
English
UGent publication?
yes
classification
C1
additional info
This paper has been nominated as a best paper candidate
copyright statement
I have transferred the copyright for this publication to the publisher
id
2093763
handle
http://hdl.handle.net/1854/LU-2093763
date created
2012-04-24 17:23:47
date last changed
2012-04-27 10:27:39
@inproceedings{2093763,
  abstract     = {Mechanistic processor performance modeling builds an analytical model from understanding the underlying mechanisms in the processor and provides fundamental insight in program-microarchitecture interactions, as well as microarchitecture structure scaling trends and interactions. Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors. We find mechanistic modeling for in-order processors to be more challenging compared to out-of-order processors because the latter are designed to hide latencies, and hence from a modeling perspective, detailed modeling of instruction execution latencies and dependencies is not required. The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch mispredictions, and achieves an average performance prediction error of 2.5\% compared to detailed cycle-accurate simulation. We extensively evaluate the model{\textquoteright}s accuracy and we demonstrate its usefulness through three applications: (i) we compare in-order versus out-of-order performance, (ii) we quantify the impact of compiler optimizations on in-order performance, and (iii) we perform a power/performance design space exploration.},
  articleno    = {2},
  author       = {Breughe, Maximilien and Eyerman, Stijn and Eeckhout, Lieven},
  booktitle    = {IEEE international symposium on performance analysis of systems and software, Proceedings},
  isbn         = {9781467311441},
  keyword      = {micro architecture,resource scaling,embedded system,compiler optimization,cpi stack,microprocessor,mechanistic model,computer architecture,design space exploration,superscalar in-order processor,performance},
  language     = {eng},
  location     = {New Brunswick, NJ, USA},
  pages        = {2:14--2:24},
  publisher    = {IEEE},
  title        = {A mechanistic performance model for superscalar in-order processors},
  year         = {2012},
}

Chicago
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. 2012. “A Mechanistic Performance Model for Superscalar In-order Processors.” In IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings, 14–24. Piscataway, NJ, USA: IEEE.
APA
Breughe, M., Eyerman, S., & Eeckhout, L. (2012). A mechanistic performance model for superscalar in-order processors. IEEE international symposium on performance analysis of systems and software, Proceedings (pp. 14–24). Presented at the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS - 2012), Piscataway, NJ, USA: IEEE.
Vancouver
1.
Breughe M, Eyerman S, Eeckhout L. A mechanistic performance model for superscalar in-order processors. IEEE international symposium on performance analysis of systems and software, Proceedings. Piscataway, NJ, USA: IEEE; 2012. p. 14–24.
MLA
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. “A Mechanistic Performance Model for Superscalar In-order Processors.” IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings. Piscataway, NJ, USA: IEEE, 2012. 14–24. Print.