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A mechanistic performance model for superscalar in-order processors

Maximilien Breughe (UGent) , Stijn Eyerman (UGent) and Lieven Eeckhout (UGent)
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Abstract
Mechanistic processor performance modeling builds an analytical model from understanding the underlying mechanisms in the processor and provides fundamental insight in program-microarchitecture interactions, as well as microarchitecture structure scaling trends and interactions. Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors. We find mechanistic modeling for in-order processors to be more challenging compared to out-of-order processors because the latter are designed to hide latencies, and hence from a modeling perspective, detailed modeling of instruction execution latencies and dependencies is not required. The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch mispredictions, and achieves an average performance prediction error of 2.5% compared to detailed cycle-accurate simulation. We extensively evaluate the model’s accuracy and we demonstrate its usefulness through three applications: (i) we compare in-order versus out-of-order performance, (ii) we quantify the impact of compiler optimizations on in-order performance, and (iii) we perform a power/performance design space exploration.
Keywords
micro architecture, resource scaling, embedded system, compiler optimization, cpi stack, microprocessor, mechanistic model, computer architecture, design space exploration, superscalar in-order processor, performance

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MLA
Breughe, Maximilien, et al. “A Mechanistic Performance Model for Superscalar In-Order Processors.” IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings, IEEE, 2012, pp. 14–24.
APA
Breughe, M., Eyerman, S., & Eeckhout, L. (2012). A mechanistic performance model for superscalar in-order processors. IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings, 14–24. Piscataway, NJ, USA: IEEE.
Chicago author-date
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. 2012. “A Mechanistic Performance Model for Superscalar In-Order Processors.” In IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings, 14–24. Piscataway, NJ, USA: IEEE.
Chicago author-date (all authors)
Breughe, Maximilien, Stijn Eyerman, and Lieven Eeckhout. 2012. “A Mechanistic Performance Model for Superscalar In-Order Processors.” In IEEE International Symposium on Performance Analysis of Systems and Software, Proceedings, 14–24. Piscataway, NJ, USA: IEEE.
Vancouver
1.
Breughe M, Eyerman S, Eeckhout L. A mechanistic performance model for superscalar in-order processors. In: IEEE international symposium on performance analysis of systems and software, Proceedings. Piscataway, NJ, USA: IEEE; 2012. p. 14–24.
IEEE
[1]
M. Breughe, S. Eyerman, and L. Eeckhout, “A mechanistic performance model for superscalar in-order processors,” in IEEE international symposium on performance analysis of systems and software, Proceedings, New Brunswick, NJ, USA, 2012, pp. 14–24.
@inproceedings{2093763,
  abstract     = {{Mechanistic processor performance modeling builds an analytical model from understanding the underlying mechanisms in the processor and provides fundamental insight in program-microarchitecture interactions, as well as microarchitecture structure scaling trends and interactions. Whereas prior work in mechanistic performance modeling focused on superscalar out-of-order processors, this paper presents a mechanistic performance model for superscalar in-order processors. We find mechanistic modeling for in-order processors to be more challenging compared to out-of-order processors because the latter are designed to hide latencies, and hence from a modeling perspective, detailed modeling of instruction execution latencies and dependencies is not required. The proposed mechanistic performance model for superscalar in-order processors models the impact of non-unit instruction execution latencies, inter-instruction dependencies, cache/TLB misses and branch mispredictions, and achieves an average performance prediction error of 2.5% compared to detailed cycle-accurate simulation. We extensively evaluate the model’s accuracy and we demonstrate its usefulness through three applications: (i) we compare in-order versus out-of-order performance, (ii) we quantify the impact of compiler optimizations on in-order performance, and (iii) we perform a power/performance design space exploration.}},
  articleno    = {{2}},
  author       = {{Breughe, Maximilien and Eyerman, Stijn and Eeckhout, Lieven}},
  booktitle    = {{IEEE international symposium on performance analysis of systems and software, Proceedings}},
  isbn         = {{9781467311441}},
  keywords     = {{micro architecture,resource scaling,embedded system,compiler optimization,cpi stack,microprocessor,mechanistic model,computer architecture,design space exploration,superscalar in-order processor,performance}},
  language     = {{eng}},
  location     = {{New Brunswick, NJ, USA}},
  pages        = {{2:14--2:24}},
  publisher    = {{IEEE}},
  title        = {{A mechanistic performance model for superscalar in-order processors}},
  year         = {{2012}},
}