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Automating reconfiguration chain generation for SRL-based run-time reconfiguration

Karel Heyse UGent, Brahim Al Farisi UGent, Karel Bruneel UGent and Dirk Stroobandt UGent (2012) LECTURE NOTES IN COMPUTER SCIENCE. 7199. p.1-12
abstract
Run-time reconfiguration (RTR) of FPGAs is mainly done using the configuration interface. However, for a certain group of designs, RTR using the shift register functionality of the LUTs is a much faster alternative than conventional RTR using the ICAP. This method requires the creation of reconfiguration chains connecting the run-time reconfigurable LUTs (SRL). In this paper, we develop and evaluate a method to generate these reconfiguration chains in an automated way so that their influence on the RTR design is minimised and the reconfiguration time is optimised. We do this by solving a constrained multiple travelling salesman problem (mTSP) based on the placement information of the run-time reconfigurable LUTs. An algorithm based on simulated annealing was developed to solve this new constrained mTSP. We show that using the proposed method, reconfiguration chains can be added with minimal influence on the clock frequency of the original design.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
keyword
Tuneable LUT Circuit, Run-Time Reconfiguration, FPGA, Shift-Register-LUT, SRL, Simulated Annealing, Multiple Travelling Salesman Problem
in
LECTURE NOTES IN COMPUTER SCIENCE
Lect. Notes Comput. Sci.
editor
Oliver CS Choy, Ray CC Cheung, Peter Athanas and Kentaro Sano
volume
7199
article_number
1
pages
1 - 12
publisher
Springer
place of publication
Berlin, Germany
conference name
8th International Symposium on Applied Reconfigurable Computing (ARC - 2012)
conference location
Hong Kong, China
conference start
2012-03-19
conference end
2012-03-23
ISSN
0302-9743
DOI
10.1007/978-3-642-28365-9_1
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
2080416
handle
http://hdl.handle.net/1854/LU-2080416
date created
2012-04-04 10:55:39
date last changed
2012-04-05 10:19:47
@inproceedings{2080416,
  abstract     = {Run-time reconfiguration (RTR) of FPGAs is mainly done using the configuration interface. However, for a certain group of designs, RTR using the shift register functionality of the LUTs is a much faster alternative than conventional RTR using the ICAP. This method requires the creation of reconfiguration chains connecting the run-time reconfigurable LUTs (SRL). In this paper, we develop and evaluate a method to generate these reconfiguration chains in an automated way so that their influence on the RTR design is minimised and the reconfiguration time is optimised. We do this by solving a constrained multiple travelling salesman problem (mTSP) based on the placement information of the run-time reconfigurable LUTs. An algorithm based on simulated annealing was developed to solve this new constrained mTSP. We show that using the proposed method, reconfiguration chains can be added with minimal influence on the clock frequency of the original design.},
  articleno    = {1},
  author       = {Heyse, Karel and Al Farisi, Brahim and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {LECTURE NOTES IN COMPUTER SCIENCE},
  editor       = {Choy, Oliver CS and Cheung, Ray CC and Athanas, Peter and Sano, Kentaro},
  issn         = {0302-9743},
  keyword      = {Tuneable LUT Circuit,Run-Time Reconfiguration,FPGA,Shift-Register-LUT,SRL,Simulated Annealing,Multiple Travelling Salesman Problem},
  language     = {eng},
  location     = {Hong Kong, China},
  pages        = {1:1--1:12},
  publisher    = {Springer},
  title        = {Automating reconfiguration chain generation for SRL-based run-time reconfiguration},
  url          = {http://dx.doi.org/10.1007/978-3-642-28365-9\_1},
  volume       = {7199},
  year         = {2012},
}

Chicago
Heyse, Karel, Brahim Al Farisi, Karel Bruneel, and Dirk Stroobandt. 2012. “Automating Reconfiguration Chain Generation for SRL-based Run-time Reconfiguration.” In Lecture Notes in Computer Science, ed. Oliver CS Choy, Ray CC Cheung, Peter Athanas, and Kentaro Sano, 7199:1–12. Berlin, Germany: Springer.
APA
Heyse, K., Al Farisi, B., Bruneel, K., & Stroobandt, D. (2012). Automating reconfiguration chain generation for SRL-based run-time reconfiguration. In O. C. Choy, R. C. Cheung, P. Athanas, & K. Sano (Eds.), LECTURE NOTES IN COMPUTER SCIENCE (Vol. 7199, pp. 1–12). Presented at the 8th International Symposium on Applied Reconfigurable Computing (ARC - 2012), Berlin, Germany: Springer.
Vancouver
1.
Heyse K, Al Farisi B, Bruneel K, Stroobandt D. Automating reconfiguration chain generation for SRL-based run-time reconfiguration. In: Choy OC, Cheung RC, Athanas P, Sano K, editors. LECTURE NOTES IN COMPUTER SCIENCE. Berlin, Germany: Springer; 2012. p. 1–12.
MLA
Heyse, Karel, Brahim Al Farisi, Karel Bruneel, et al. “Automating Reconfiguration Chain Generation for SRL-based Run-time Reconfiguration.” Lecture Notes in Computer Science. Ed. Oliver CS Choy et al. Vol. 7199. Berlin, Germany: Springer, 2012. 1–12. Print.