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Dynamic data folding with parameterizable FPGA configurations

Karel Bruneel UGent, Wim Heirman UGent and Dirk Stroobandt UGent (2011) ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. 16(4).
abstract
In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter values change. This technique is called dynamic data folding. The specialized circuits are smaller and faster than their generic counterparts. However; the overhead involved in generating the configurations for the specialized circuits at runtime is very large when conventional tools are used, and this overhead will in many cases negate the benefit of using optimized configurations. This article introduces an automatic method for generating runtime parameterizable configurations from arbitrary Boolean circuits. These configurations, in which some of the configuration bits are expressed as a closed-form Boolean expression of a set of parameters, enable very fast run-time specialization, since specialization only involves evaluating these expressions. Our approach is validated on a ternary content-addressable memory (TCAM). We show that the specialized configurations, produced by our method use 2.82 times fewer LUTs than the generic configuration, and even 1.41 times fewer LUTs than the implementation generated by Xilinx Coregen. Moreover, while Coregen needs hand-crafted generators for each type of circuit, our toolflow can be applied to any VHDL design. Using our automatic and generally applicable method, run-time hardware optimization suddenly becomes feasible for a large class of applications.
Please use this url to cite or link to this publication:
author
organization
year
type
journalArticle (original)
publication status
published
subject
keyword
dynamic data folding, Automatic hardware synthesis, FPGA, run-time reconfiguration
journal title
ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS
ACM Transact. Des. Automat. Electron. Syst.
volume
16
issue
4
article_number
43
pages
29 pages
Web of Science type
Article
Web of Science id
000297137800007
JCR category
COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
JCR impact factor
0.811 (2011)
JCR rank
28/50 (2011)
JCR quartile
3 (2011)
ISSN
1084-4309
DOI
10.1145/2003695.2003703
language
English
UGent publication?
yes
classification
A1
copyright statement
I have transferred the copyright for this publication to the publisher
id
2019456
handle
http://hdl.handle.net/1854/LU-2019456
date created
2012-02-03 16:21:42
date last changed
2012-03-20 08:50:28
@article{2019456,
  abstract     = {In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter values change. This technique is called dynamic data folding. The specialized circuits are smaller and faster than their generic counterparts. However; the overhead involved in generating the configurations for the specialized circuits at runtime is very large when conventional tools are used, and this overhead will in many cases negate the benefit of using optimized configurations. This article introduces an automatic method for generating runtime parameterizable configurations from arbitrary Boolean circuits. These configurations, in which some of the configuration bits are expressed as a closed-form Boolean expression of a set of parameters, enable very fast run-time specialization, since specialization only involves evaluating these expressions. Our approach is validated on a ternary content-addressable memory (TCAM). We show that the specialized configurations, produced by our method use 2.82 times fewer LUTs than the generic configuration, and even 1.41 times fewer LUTs than the implementation generated by Xilinx Coregen. Moreover, while Coregen needs hand-crafted generators for each type of circuit, our toolflow can be applied to any VHDL design. Using our automatic and generally applicable method, run-time hardware optimization suddenly becomes feasible for a large class of applications.},
  articleno    = {43},
  author       = {Bruneel, Karel and Heirman, Wim and Stroobandt, Dirk},
  issn         = {1084-4309},
  journal      = {ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS},
  keyword      = {dynamic data folding,Automatic hardware synthesis,FPGA,run-time reconfiguration},
  language     = {eng},
  number       = {4},
  pages        = {29},
  title        = {Dynamic data folding with parameterizable FPGA configurations},
  url          = {http://dx.doi.org/10.1145/2003695.2003703},
  volume       = {16},
  year         = {2011},
}

Chicago
Bruneel, Karel, Wim Heirman, and Dirk Stroobandt. 2011. “Dynamic Data Folding with Parameterizable FPGA Configurations.” Acm Transactions on Design Automation of Electronic Systems 16 (4).
APA
Bruneel, K., Heirman, W., & Stroobandt, D. (2011). Dynamic data folding with parameterizable FPGA configurations. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 16(4).
Vancouver
1.
Bruneel K, Heirman W, Stroobandt D. Dynamic data folding with parameterizable FPGA configurations. ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS. 2011;16(4).
MLA
Bruneel, Karel, Wim Heirman, and Dirk Stroobandt. “Dynamic Data Folding with Parameterizable FPGA Configurations.” ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS 16.4 (2011): n. pag. Print.