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A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS

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Abstract
A 4th-order 40MHz Bandwidth 12bit continuous-time delta-sigma modulator is presented in this paper. A shaped SC DAC with reduced peak current is proposed to relax the OTA slewing requirement, consuming no extra hardware or power. The DAC static and dynamic mismatches are eliminated by lookup table based digital calibration. With 1.2V supply and 69.6mW power in 90nm CMOS, the modulator achieves excellent SFDR of 84.2dB and 72.9dB peak SNDR at 960MHz clock frequency, corresponding to a FoM of 0.24pJ/Step. The core circuit area is about 0.28mm2.

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Chicago
Xinpeng Xing, Xinpeng, Maarten De Bock, Pieter Rombouts, and Georges Gielen. 2011. “A 40MHz 12bit 84.2dB-SFDR Continuous-time Delta-sigma Modulator in 90nm CMOS.” In IEEE Asian Solid-state Circuits Conference, Proceedings, 249–252. IEEE.
APA
Xinpeng Xing, X., De Bock, M., Rombouts, P., & Gielen, G. (2011). A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS. IEEE Asian solid-state circuits conference, Proceedings (pp. 249–252). Presented at the IEEE Asian Solid-State Circuits Conference, IEEE.
Vancouver
1.
Xinpeng Xing X, De Bock M, Rombouts P, Gielen G. A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS. IEEE Asian solid-state circuits conference, Proceedings. IEEE; 2011. p. 249–52.
MLA
Xinpeng Xing, Xinpeng, Maarten De Bock, Pieter Rombouts, et al. “A 40MHz 12bit 84.2dB-SFDR Continuous-time Delta-sigma Modulator in 90nm CMOS.” IEEE Asian Solid-state Circuits Conference, Proceedings. IEEE, 2011. 249–252. Print.
@inproceedings{2014883,
  abstract     = {A 4th-order 40MHz Bandwidth 12bit continuous-time delta-sigma modulator is presented in this paper. A shaped SC DAC with reduced peak current is proposed to relax the OTA slewing requirement, consuming no extra hardware or power. The DAC static and dynamic mismatches are eliminated by lookup table based digital calibration. With 1.2V supply and 69.6mW power in 90nm CMOS, the modulator achieves excellent SFDR of 84.2dB and 72.9dB peak SNDR at 960MHz clock frequency, corresponding to a FoM of 0.24pJ/Step. The core circuit area is about 0.28mm2.},
  author       = {Xinpeng Xing, Xinpeng and De Bock, Maarten and Rombouts, Pieter and Gielen, Georges},
  booktitle    = {IEEE Asian solid-state circuits conference, Proceedings},
  isbn         = {9781457717840},
  language     = {eng},
  location     = {Jeju, Korea},
  pages        = {249--252},
  publisher    = {IEEE},
  title        = {A 40MHz 12bit 84.2dB-SFDR continuous-time delta-sigma modulator in 90nm CMOS},
  url          = {http://dx.doi.org/10.1109/ASSCC.2011.6123557},
  year         = {2011},
}

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