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Abstract
Coarse-Grained Reconfigurable Array (CGRA) processors accelerate inner loops of applications by exploiting instructionlevel parallelism (ILP) and in some cases also data-level and task-level parallelism (DLP & TLP). The aim of this tutorial is to give insight in CGRA architectures and their compilation techniques to exploit parallelism. These topics will be covered: middot Polymorphic pipeline arrays, expanding coarse-grained arrays beyond innermost loops (Scott Mahlke, University of Michigan) middot Code-generation for coarse-grained arrays: flexibility and programmer productivity (Bjorn De Sutter, Ghent University) middot Memory-aware compilation techniques for CGRAs (Aviral Shrivastava, Arizona State University) middot Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays (Frank Hannig, University of Erlangen-Nuremberg).
Keywords
reconfigurable architectures, program compilers

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MLA
Vander Aa, Tom, Praveen Raghavan, Scott Mahlke, et al. “Compilation Techniques for CGRAs: Exploring All Parallelization Approaches.” 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). New York, NY, USA: Association for Computing Machinery (ACM), 2010. 185–186. Print.
APA
Vander Aa, T., Raghavan, P., Mahlke, S., De Sutter, B., Shrivastava, A., & Hannig, F. (2010). Compilation techniques for CGRAs: exploring all parallelization approaches. 2010 IEEE/ACM/IFIP International conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) (pp. 185–186). Presented at the 2010 IEEE/ACM/IFIP International conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), New York, NY, USA: Association for Computing Machinery (ACM).
Chicago author-date
Vander Aa, Tom, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava, and Frank Hannig. 2010. “Compilation Techniques for CGRAs: Exploring All Parallelization Approaches.” In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 185–186. New York, NY, USA: Association for Computing Machinery (ACM).
Chicago author-date (all authors)
Vander Aa, Tom, Praveen Raghavan, Scott Mahlke, Bjorn De Sutter, Aviral Shrivastava, and Frank Hannig. 2010. “Compilation Techniques for CGRAs: Exploring All Parallelization Approaches.” In 2010 IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 185–186. New York, NY, USA: Association for Computing Machinery (ACM).
Vancouver
1.
Vander Aa T, Raghavan P, Mahlke S, De Sutter B, Shrivastava A, Hannig F. Compilation techniques for CGRAs: exploring all parallelization approaches. 2010 IEEE/ACM/IFIP International conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS). New York, NY, USA: Association for Computing Machinery (ACM); 2010. p. 185–6.
IEEE
[1]
T. Vander Aa, P. Raghavan, S. Mahlke, B. De Sutter, A. Shrivastava, and F. Hannig, “Compilation techniques for CGRAs: exploring all parallelization approaches,” in 2010 IEEE/ACM/IFIP International conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Scottsdale, AZ, USA, 2010, pp. 185–186.
@inproceedings{2006700,
  abstract     = {Coarse-Grained Reconfigurable Array (CGRA) processors accelerate inner loops of applications by exploiting instructionlevel parallelism (ILP) and in some cases also data-level and task-level parallelism (DLP & TLP). The aim of this tutorial is to give insight in CGRA architectures and their compilation techniques to exploit parallelism. These topics will be covered: middot Polymorphic pipeline arrays, expanding coarse-grained arrays beyond innermost loops (Scott Mahlke, University of Michigan) middot Code-generation for coarse-grained arrays: flexibility and programmer productivity (Bjorn De Sutter, Ghent University) middot Memory-aware compilation techniques for CGRAs (Aviral Shrivastava, Arizona State University) middot Retargetable Mapping of Loop Programs on Coarse-grained Reconfigurable Arrays (Frank Hannig, University of Erlangen-Nuremberg).},
  author       = {Vander Aa, Tom and Raghavan, Praveen and Mahlke, Scott and De Sutter, Bjorn and Shrivastava, Aviral and Hannig, Frank},
  booktitle    = {2010 IEEE/ACM/IFIP International conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
  isbn         = {9781605589053},
  keywords     = {reconfigurable architectures,program compilers},
  language     = {eng},
  location     = {Scottsdale, AZ, USA},
  pages        = {185--186},
  publisher    = {Association for Computing Machinery (ACM)},
  title        = {Compilation techniques for CGRAs: exploring all parallelization approaches},
  url          = {http://dx.doi.org/10.1145/1878961.1878995},
  year         = {2010},
}

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