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System-level power/performance evaluation of 3D stacked DRAMs for mobile applications

Marco Facchini, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini and Pol Marchal (2009) Design, Automation and Test in Europe Conference and Expo. p.923-928
abstract
Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottle-neck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.
Please use this url to cite or link to this publication:
author
organization
year
type
conference (proceedingsPaper)
publication status
published
subject
in
Design, Automation and Test in Europe Conference and Expo
issue title
DATE 2009 : design, automation and test in Europe conference and exhibition
pages
923 - 928
publisher
IEEE
place of publication
New York, NY, USA
conference name
Design, Automation and Test in Europe conference and exhibition (DATE 2009)
conference location
Nice, France
conference start
2009-04-20
conference end
2009-04-24
Web of Science type
Proceedings Paper
Web of Science id
000273246700166
ISSN
1530-1591
ISBN
9781424437818
language
English
UGent publication?
no
classification
P1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1999390
handle
http://hdl.handle.net/1854/LU-1999390
alternative location
http://www.date-conference.com/archive/conference/proceedings/PAPERS/2009/DATE09/PDFFILES/08.2_3.PDF
date created
2012-01-22 19:57:08
date last changed
2017-01-02 09:53:11
@inproceedings{1999390,
  abstract     = {Convergence of communication, consumer applications and computing within mobile systems pushes memory requirements both in terms of size, bandwidth and power consumption. The existing solution for the memory bottle-neck is to increase the amount of on-chip memory. However, this solution is becoming prohibitively expensive, allowing 3D stacked DRAM to become an interesting alternative for mobile applications. In this paper, we examine the power/performance benefits for three different 3D stacked DRAM scenarios. Our high-level memory and Through Silicon Via (TSV) models have been calibrated on state-of-the-art industrial processes. We model the integration of a logic die with TSVs on top of both an existing DRAM and a DRAM with redesigned transceivers for 3D. Finally, we take advantage of the interconnect density enabled by 3D technology to analyze an ultra-wide memory interface. Experimental results confirm that TSV-based 3D integration is a promising technology option for future mobile applications, and that its full potential can be unleashed by jointly optimizing memory architecture and interface logic.},
  author       = {Facchini, Marco and Carlson, Trevor and Vignon, Anselme and Palkovic, Martin and Catthoor, Francky and Dehaene, Wim and Benini, Luca and Marchal, Pol},
  booktitle    = {Design, Automation and Test in Europe Conference and Expo},
  isbn         = {9781424437818},
  issn         = {1530-1591},
  language     = {eng},
  location     = {Nice, France},
  pages        = {923--928},
  publisher    = {IEEE},
  title        = {System-level power/performance evaluation of 3D stacked DRAMs for mobile applications},
  url          = {http://www.date-conference.com/archive/conference/proceedings/PAPERS/2009/DATE09/PDFFILES/08.2\_3.PDF},
  year         = {2009},
}

Chicago
Facchini, Marco, Trevor Carlson, Anselme Vignon, Martin Palkovic, Francky Catthoor, Wim Dehaene, Luca Benini, and Pol Marchal. 2009. “System-level Power/performance Evaluation of 3D Stacked DRAMs for Mobile Applications.” In Design, Automation and Test in Europe Conference and Expo, 923–928. New York, NY, USA: IEEE.
APA
Facchini, M., Carlson, T., Vignon, A., Palkovic, M., Catthoor, F., Dehaene, W., Benini, L., et al. (2009). System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. Design, Automation and Test in Europe Conference and Expo (pp. 923–928). Presented at the Design, Automation and Test in Europe conference and exhibition (DATE 2009), New York, NY, USA: IEEE.
Vancouver
1.
Facchini M, Carlson T, Vignon A, Palkovic M, Catthoor F, Dehaene W, et al. System-level power/performance evaluation of 3D stacked DRAMs for mobile applications. Design, Automation and Test in Europe Conference and Expo. New York, NY, USA: IEEE; 2009. p. 923–8.
MLA
Facchini, Marco, Trevor Carlson, Anselme Vignon, et al. “System-level Power/performance Evaluation of 3D Stacked DRAMs for Mobile Applications.” Design, Automation and Test in Europe Conference and Expo. New York, NY, USA: IEEE, 2009. 923–928. Print.