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How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems

Dirk Stroobandt (UGent) and Karel Bruneel (UGent)
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Abstract
Adaptive embedded systems are currently investigated as an answer to more stringent requirements on low power, in combination with significant performance. It is clear that runtime adaptation can offer benefits to embedded systems over static implementations as the architecture itself can be tuned to the problem at hand. Such architecture specialisation should be done fast enough so that the overhead of adapting the system does not overshadow the benefits obtained by the adaptivity. In this paper, we propose a methodology for FPGA design that allows such a fast reconfiguration for dynamic datafolding applications. Dynamic Data Folding (DDF) is a technique to dynamically specialize an FPGA configuration according to the values of a set of parameters. The general idea of DDF is that each time the parameter values change, the device is reconfigured with a configuration that is specialized for the new parameter values. Since specialized configurations are smaller and faster than their generic counterpart, the hope is that their corresponding system implementation will be more cost efficient. In this paper, we show that DDF can be implemented on current commercial FPGAs by using the parameterizable run-time reconfiguration methodology. This methodology comprises a tool flow that automatically transforms DDF applications to a runtime adaptive implementation. Experimental results with this tool flow show that we can reap the benefits (smaller area and faster clocks) without too much reconfiguration overhead.
Keywords
FPGA, Run-time reconfiguration, Dynamic Data Folding, Automatic hardware synthesis

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MLA
Stroobandt, Dirk, and Karel Bruneel. “How Parameterizable Run-time FPGA Reconfiguration Can Benefit Adaptive Embedded Systems.” Worldcomp 2011, Proceedings. Ed. Toomas Plaks. CSREA Press, 2011. 184–194. Print.
APA
Stroobandt, D., & Bruneel, K. (2011). How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems. In T. Plaks (Ed.), Worldcomp 2011, Proceedings (pp. 184–194). Presented at the 2011 International conference on Engineering of Reconfigurable Systems and Algorithms (ERSA 2011); at the 2011 World congress in Computer Science, Computer Engineering and Applied Computing (Worldcomp 2011), CSREA Press.
Chicago author-date
Stroobandt, Dirk, and Karel Bruneel. 2011. “How Parameterizable Run-time FPGA Reconfiguration Can Benefit Adaptive Embedded Systems.” In Worldcomp 2011, Proceedings, ed. Toomas Plaks, 184–194. CSREA Press.
Chicago author-date (all authors)
Stroobandt, Dirk, and Karel Bruneel. 2011. “How Parameterizable Run-time FPGA Reconfiguration Can Benefit Adaptive Embedded Systems.” In Worldcomp 2011, Proceedings, ed. Toomas Plaks, 184–194. CSREA Press.
Vancouver
1.
Stroobandt D, Bruneel K. How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems. In: Plaks T, editor. Worldcomp 2011, Proceedings. CSREA Press; 2011. p. 184–94.
IEEE
[1]
D. Stroobandt and K. Bruneel, “How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems,” in Worldcomp 2011, Proceedings, Las Vegas, NV, USA, 2011, pp. 184–194.
@inproceedings{1870314,
  abstract     = {Adaptive embedded systems are currently investigated as an answer to more stringent requirements on low power, in combination with significant performance. It is clear that runtime adaptation can offer benefits to embedded systems over static implementations as the architecture itself can be tuned to the problem at hand. Such architecture specialisation should be done fast enough so that the overhead of adapting the system does not overshadow the benefits obtained by the adaptivity. In this paper, we propose a methodology for FPGA design that allows such a fast reconfiguration for dynamic datafolding applications. Dynamic Data Folding (DDF) is a technique to dynamically specialize an FPGA configuration according to the values of a set of parameters. The general idea of DDF is that each time the parameter values change, the device is reconfigured with a configuration that is specialized for the new parameter values. Since specialized configurations are smaller and faster than their generic counterpart, the hope is that their corresponding system implementation will be more cost efficient. In this paper, we show that DDF can be implemented on current commercial FPGAs by using the parameterizable run-time reconfiguration methodology. This methodology comprises a tool flow that automatically transforms DDF applications to a runtime adaptive implementation. Experimental results with this tool flow show that we can reap the benefits (smaller area and faster clocks) without too much reconfiguration overhead.},
  author       = {Stroobandt, Dirk and Bruneel, Karel},
  booktitle    = {Worldcomp 2011, Proceedings},
  editor       = {Plaks, Toomas},
  isbn         = {9781601321770},
  keywords     = {FPGA,Run-time reconfiguration,Dynamic Data Folding,Automatic hardware synthesis},
  language     = {eng},
  location     = {Las Vegas, NV, USA},
  pages        = {184--194},
  publisher    = {CSREA Press},
  title        = {How parameterizable run-time FPGA reconfiguration can benefit adaptive embedded systems},
  year         = {2011},
}