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Towards a more efficient run-time FPGA configuration generation

Fatma Mostafa Mohamed Ahmed Abouelella, Karel Bruneel UGent and Dirk Stroobandt UGent (2010) Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts. p.113-116
abstract
Parameterizable configurations are regular FPGA configurations in which some of the configuration bits are expressed as a Boolean function of a set of parameters. These configurations can rapidly be transformed to a specialized configuration by evaluating the Boolean functions for a specific set of parameter values and are therefore ideal for use in run-time reconfigurable systems. In this paper, the concept of Parameterizable Bitstream (PBS) is introduced to accommodate the use of parameterizable configurations in commercial FPGAs. A stack machine system is implemented that can efficiently transform a PBS to a specialized configuration.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
published
subject
in
Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts
editor
Koen De Bosschere UGent
pages
113 - 116
publisher
European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)
conference name
6th International summer school on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2010)
conference location
Terrassa, Spain
conference start
2010-07-11
conference end
2010-07-17
ISBN
9789038216317
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1864315
handle
http://hdl.handle.net/1854/LU-1864315
date created
2011-08-01 15:45:06
date last changed
2016-12-19 15:37:05
@inproceedings{1864315,
  abstract     = {Parameterizable configurations are regular FPGA configurations in which some of the configuration bits are expressed as a Boolean function of a set of parameters. These configurations can rapidly be transformed to a specialized configuration by evaluating the Boolean functions for a specific set of parameter values and are therefore ideal for use in run-time reconfigurable systems. In this paper, the concept of Parameterizable Bitstream (PBS) is introduced to accommodate the use of parameterizable configurations in commercial FPGAs. A stack machine system is implemented that can efficiently transform a PBS to a specialized configuration.},
  author       = {Mostafa Mohamed Ahmed Abouelella, Fatma and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts},
  editor       = {De Bosschere, Koen},
  isbn         = {9789038216317},
  language     = {eng},
  location     = {Terrassa, Spain},
  pages        = {113--116},
  publisher    = {European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC)},
  title        = {Towards a more efficient run-time FPGA configuration generation},
  year         = {2010},
}

Chicago
Mostafa Mohamed Ahmed Abouelella, Fatma, Karel Bruneel, and Dirk Stroobandt. 2010. “Towards a More Efficient Run-time FPGA Configuration Generation.” In Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International Summer School, Poster Abstracts, ed. Koen De Bosschere, 113–116. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).
APA
Mostafa Mohamed Ahmed Abouelella, F., Bruneel, K., & Stroobandt, D. (2010). Towards a more efficient run-time FPGA configuration generation. In K. De Bosschere (Ed.), Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts (pp. 113–116). Presented at the 6th International summer school on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES 2010), European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC).
Vancouver
1.
Mostafa Mohamed Ahmed Abouelella F, Bruneel K, Stroobandt D. Towards a more efficient run-time FPGA configuration generation. In: De Bosschere K, editor. Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International summer school, Poster abstracts. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC); 2010. p. 113–6.
MLA
Mostafa Mohamed Ahmed Abouelella, Fatma, Karel Bruneel, and Dirk Stroobandt. “Towards a More Efficient Run-time FPGA Configuration Generation.” Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems, 6th International Summer School, Poster Abstracts. Ed. Koen De Bosschere. European Network of Excellence on High Performance and Embedded Architecture and Compilation (HiPEAC), 2010. 113–116. Print.