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Memory-efficient and fast run-time reconfiguration of regularly structured designs

Brahim Al Farisi UGent, Karel Heyse UGent, Karel Bruneel UGent and Dirk Stroobandt UGent (2011) Field Programmable Logic and Applications, 21st International conference, Proceedings.
abstract
Previous work has shown that run-time reconfiguration of FPGAs benefits greatly from the use of Tunable LUT (TLUT) circuits. These can be rapidly transformed into a specialized LUT circuit and are also very memory efficient when representing regularly structured designs, where the same hardware module is instantiated many times. However, the memory requirements and reconfiguration time of a run-time reconfigurable application are also dependent on the reconfiguration mechanism. In this paper, we will show that the memory requirements of conventional ICAP reconfiguration grow very fast with the number of modules, resulting in excessive memory usage. We propose to use Shift-Register-LUT (SRL) reconfiguration which is faster and results in a memory usage that is independent of the number of modules.
Please use this url to cite or link to this publication:
author
organization
year
type
conference
publication status
in press
subject
keyword
FPGA, Run-time Reconfiguration, Tunable LUT circuit, ICAP, SRL
in
Field Programmable Logic and Applications, 21st International conference, Proceedings
pages
6 pages
conference name
21st International Conference on Field Programmable Logic and Applications (FPL 2011)
conference location
Chania, Crete, Greece
conference start
2011-09-05
conference end
2011-09-07
language
English
UGent publication?
yes
classification
C1
copyright statement
I have transferred the copyright for this publication to the publisher
id
1864276
handle
http://hdl.handle.net/1854/LU-1864276
date created
2011-08-01 15:02:18
date last changed
2011-09-08 00:31:20
@inproceedings{1864276,
  abstract     = {Previous work has shown that run-time reconfiguration of FPGAs benefits greatly from the use of Tunable LUT (TLUT) circuits. These can be rapidly transformed into a specialized LUT circuit and are also very memory efficient when representing regularly structured designs, where the same hardware module is instantiated many times. However, the memory requirements and reconfiguration time of a run-time reconfigurable application are also dependent on the reconfiguration mechanism. In this paper, we will show that the memory requirements of conventional ICAP reconfiguration grow very fast with the number of modules, resulting in excessive memory usage. We propose to use Shift-Register-LUT (SRL) reconfiguration which is faster and results in a memory usage that is independent of the number of modules.},
  author       = {Al Farisi, Brahim and Heyse, Karel and Bruneel, Karel and Stroobandt, Dirk},
  booktitle    = {Field Programmable Logic and Applications, 21st International conference, Proceedings},
  keyword      = {FPGA,Run-time Reconfiguration,Tunable LUT circuit,ICAP,SRL},
  language     = {eng},
  location     = {Chania, Crete, Greece},
  pages        = {6},
  title        = {Memory-efficient and fast run-time reconfiguration of regularly structured designs},
  year         = {2011},
}

Chicago
Al Farisi, Brahim, Karel Heyse, Karel Bruneel, and Dirk Stroobandt. 2011. “Memory-efficient and Fast Run-time Reconfiguration of Regularly Structured Designs.” In Field Programmable Logic and Applications, 21st International Conference, Proceedings.
APA
Al Farisi, B., Heyse, K., Bruneel, K., & Stroobandt, D. (2011). Memory-efficient and fast run-time reconfiguration of regularly structured designs. Field Programmable Logic and Applications, 21st International conference, Proceedings. Presented at the 21st International Conference on Field Programmable Logic and Applications (FPL 2011).
Vancouver
1.
Al Farisi B, Heyse K, Bruneel K, Stroobandt D. Memory-efficient and fast run-time reconfiguration of regularly structured designs. Field Programmable Logic and Applications, 21st International conference, Proceedings. 2011.
MLA
Al Farisi, Brahim, Karel Heyse, Karel Bruneel, et al. “Memory-efficient and Fast Run-time Reconfiguration of Regularly Structured Designs.” Field Programmable Logic and Applications, 21st International Conference, Proceedings. 2011. Print.