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A performance counter architecture for computing accurate CPI components

(2006) ACM SIGPLAN NOTICES. 41(11). p.175-184
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Abstract
A common way of representing processor performance is to use Cycles per Instruction (CPI) `stacks' which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight into the behavior of an application on a given microprocessor; consequently, they are widely used by software application developers and computer architects. However, computing CPI stacks on superscalar out-of-order processors is challenging because of various overlaps among execution and miss events ( cache misses, TLB misses, and branch mispredictions). This paper shows that meaningful and accurate CPI stacks can be computed for superscalar out-of-order processors. Using interval analysis, a novel method for analyzing out-of-order processor performance, we gain understanding into the performance impact of the various miss events. Based on this understanding, we propose a novel way of architecting hardware performance counters for building accurate CPI stacks. The additional hardware for implementing these counters is limited and comparable to existing hardware performance counter architectures while being significantly more accurate than previous approaches.
Keywords
super-scalar processor performance modeling, hardware performance counter architecture

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Chicago
Eyerman, Stijn, Lieven Eeckhout, Tejas Karkhanis, and James E Smith. 2006. “A Performance Counter Architecture for Computing Accurate CPI Components.” Acm Sigplan Notices 41 (11): 175–184.
APA
Eyerman, S., Eeckhout, L., Karkhanis, T., & Smith, J. E. (2006). A performance counter architecture for computing accurate CPI components. ACM SIGPLAN NOTICES, 41(11), 175–184.
Vancouver
1.
Eyerman S, Eeckhout L, Karkhanis T, Smith JE. A performance counter architecture for computing accurate CPI components. ACM SIGPLAN NOTICES. 2006;41(11):175–84.
MLA
Eyerman, Stijn, Lieven Eeckhout, Tejas Karkhanis, et al. “A Performance Counter Architecture for Computing Accurate CPI Components.” ACM SIGPLAN NOTICES 41.11 (2006): 175–184. Print.
@article{1579395,
  abstract     = {A common way of representing processor performance is to use Cycles per Instruction (CPI) `stacks' which break performance into a baseline CPI plus a number of individual miss event CPI components. CPI stacks can be very helpful in gaining insight into the behavior of an application on a given microprocessor; consequently, they are widely used by software application developers and computer architects. However, computing CPI stacks on superscalar out-of-order processors is challenging because of various overlaps among execution and miss events ( cache misses, TLB misses, and branch mispredictions). This paper shows that meaningful and accurate CPI stacks can be computed for superscalar out-of-order processors. Using interval analysis, a novel method for analyzing out-of-order processor performance, we gain understanding into the performance impact of the various miss events. Based on this understanding, we propose a novel way of architecting hardware performance counters for building accurate CPI stacks. The additional hardware for implementing these counters is limited and comparable to existing hardware performance counter architectures while being significantly more accurate than previous approaches.},
  author       = {Eyerman, Stijn and Eeckhout, Lieven and Karkhanis, Tejas and Smith, James E},
  issn         = {0362-1340},
  journal      = {ACM SIGPLAN NOTICES},
  keyword      = {super-scalar processor performance modeling,hardware performance counter architecture},
  language     = {eng},
  number       = {11},
  pages        = {175--184},
  title        = {A performance counter architecture for computing accurate CPI components},
  url          = {http://dx.doi.org/10.1145/1168918.1168880},
  volume       = {41},
  year         = {2006},
}

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