Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware
- Author
- Stijn Eyerman (UGent) , Kenneth Hoste (UGent) and Lieven Eeckhout (UGent)
- Organization
- Abstract
- Analytical processor performance modeling has received increased interest over the past few years. There are basically two approaches to constructing an analytical model: mechanistic modeling and empirical modeling. Mechanistic modeling builds up an analytical model starting from a basic understanding of the underlying system - white-box approach - whereas empirical modeling constructs an analytical model through statistical inference and machine learning from training data, e.g., regression modeling or neural networks - black-box approach. While an empirical model is typically easier to construct, it provides less insight than a mechanistic model. This paper bridges the gap between mechanistic and empirical modeling through hybrid mechanistic-empirical modeling (gray-box modeling). Starting from a generic, parameterized performance model that is inspired by mechanistic modeling, regression modeling infers the unknown parameters, alike empirical modeling. Mechanistic-empirical models combine the best of both worlds: they provide insight (like mechanistic models) while being easy to construct (like empirical models). We build mechanistic-empirical performance models for three commercial processor cores, the Intel Pentium 4, Core 2 and Core il, using SPEC CPU2000 and CPU2006, and report average prediction errors between 9% and 13%. In addition, we demonstrate that the mechanistic-empirical model is more robust and less subject to overfitting than purely empirical models. A key feature of the proposed mechanistic-empirical model is that it enables constructing CPI stacks on real hardware, which provide insight in commercial processor performance and which offer opportunities for software and hardware optimization and analysis.
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Citation
Please use this url to cite or link to this publication: http://hdl.handle.net/1854/LU-1354077
- MLA
- Eyerman, Stijn, et al. “Mechanistic-Empirical Processor Performance Modeling for Constructing CPI Stacks on Real Hardware.” 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011), IEEE, 2011, pp. 216–26, doi:10.1109/ISPASS.2011.5762738.
- APA
- Eyerman, S., Hoste, K., & Eeckhout, L. (2011). Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011), 216–226. https://doi.org/10.1109/ISPASS.2011.5762738
- Chicago author-date
- Eyerman, Stijn, Kenneth Hoste, and Lieven Eeckhout. 2011. “Mechanistic-Empirical Processor Performance Modeling for Constructing CPI Stacks on Real Hardware.” In 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011), 216–26. Los Alamitos, CA, USA: IEEE. https://doi.org/10.1109/ISPASS.2011.5762738.
- Chicago author-date (all authors)
- Eyerman, Stijn, Kenneth Hoste, and Lieven Eeckhout. 2011. “Mechanistic-Empirical Processor Performance Modeling for Constructing CPI Stacks on Real Hardware.” In 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011), 216–226. Los Alamitos, CA, USA: IEEE. doi:10.1109/ISPASS.2011.5762738.
- Vancouver
- 1.Eyerman S, Hoste K, Eeckhout L. Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware. In: 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011). Los Alamitos, CA, USA: IEEE; 2011. p. 216–26.
- IEEE
- [1]S. Eyerman, K. Hoste, and L. Eeckhout, “Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware,” in 2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011), Austin, TX, USA, 2011, pp. 216–226.
@inproceedings{1354077,
abstract = {{Analytical processor performance modeling has received increased interest over the past few years. There are basically two approaches to constructing an analytical model: mechanistic modeling and empirical modeling. Mechanistic modeling builds up an analytical model starting from a basic understanding of the underlying system - white-box approach - whereas empirical modeling constructs an analytical model through statistical inference and machine learning from training data, e.g., regression modeling or neural networks - black-box approach. While an empirical model is typically easier to construct, it provides less insight than a mechanistic model. This paper bridges the gap between mechanistic and empirical modeling through hybrid mechanistic-empirical modeling (gray-box modeling). Starting from a generic, parameterized performance model that is inspired by mechanistic modeling, regression modeling infers the unknown parameters, alike empirical modeling. Mechanistic-empirical models combine the best of both worlds: they provide insight (like mechanistic models) while being easy to construct (like empirical models). We build mechanistic-empirical performance models for three commercial processor cores, the Intel Pentium 4, Core 2 and Core il, using SPEC CPU2000 and CPU2006, and report average prediction errors between 9% and 13%. In addition, we demonstrate that the mechanistic-empirical model is more robust and less subject to overfitting than purely empirical models. A key feature of the proposed mechanistic-empirical model is that it enables constructing CPI stacks on real hardware, which provide insight in commercial processor performance and which offer opportunities for software and hardware optimization and analysis.}},
articleno = {{11975392}},
author = {{Eyerman, Stijn and Hoste, Kenneth and Eeckhout, Lieven}},
booktitle = {{2011 IEEE International Symposium on Performance Analysis of Systems & Software (ISPASS 2011)}},
isbn = {{9781612843674}},
language = {{eng}},
location = {{Austin, TX, USA}},
pages = {{11975392:216--11975392:226}},
publisher = {{IEEE}},
title = {{Mechanistic-empirical processor performance modeling for constructing CPI stacks on real hardware}},
url = {{http://doi.org/10.1109/ISPASS.2011.5762738}},
year = {{2011}},
}
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